Data Structures |
| struct | _xsp3_feature |
| struct | _xspress3_saved_config |
| struct | _UDPconnection |
| struct | _XSPROI |
| struct | _ChannelDTC |
| struct | _Histogram |
| struct | _Histogram::window_limits |
| struct | _XSP3Path |
| struct | trigger_b_setttings |
| struct | trigger_c_setttings |
| struct | pileup_times_struct |
| struct | _fan_log |
| struct | _fan_cont |
Defines |
| #define | XSP3_CONF_SOFTWARE_ROI_LUT 0 |
| #define | XSP3_CONF_ACCUMULATE_RESET_TICKS 0 |
| #define | XSP3_CONF_ALL_GOOD_FROM_MCA 0 |
| #define | XSP3_SGX_SOFTWARE 0 |
| | Enable SGX processing in software (currently firmware option).
|
| #define | FEM_SINGLE 0 |
| #define | FEM_COMPOSITE 1 |
| #define | XSP3_BINS_PER_MCA 4096 |
| #define | XSP3_SW_NUM_SCALERS 9 |
| #define | XSP_SW_SCALER_LIVE_TICKS 0 |
| | Total exposure time, may show lower than programmed time if data packets are dropped. Can beuse to scale for dropped packets.
|
| #define | XSP_SW_SCALER_RESET_TICKS 1 |
| | Time in Reset or reset crostalk glitch padding.
|
| #define | XSP_SW_SCALER_NUM_RESETS 2 |
| | Number of Resets.
|
| #define | XSP_SW_SCALER_ALL_EVENT 3 |
| | Number of all event triggers.
|
| #define | XSP_SW_SCALER_ALL_GOOD 4 |
| | Number of events with positivie energy > Good threshold.
|
| #define | XSP_SW_SCALER_IN_WINDOW0 5 |
| | Number of events in window 0.
|
| #define | XSP_SW_SCALER_IN_WINDOW1 6 |
| | Number of events in window 1.
|
| #define | XSP_SW_SCALER_PILEUP 7 |
| | Number of events detected as pileup.
|
| #define | XSP_SW_SCALER_TOTAL_TICKS 8 |
| | Total time in 80MHz ticks of exposure, even if some packets are dropped.
|
| #define | XSP3_SOFT_SCALER_TOTAL_TICKS 8 |
| | Total integration time ticks.
|
| #define | XSP3_NUM_SOFT_SCALERS 9 |
| #define | XSP3_SOFT_SCALER_LIVE_TICKS 0 |
| | Total integration time in received packets, may may less than total ticks due to dropped packets.
|
| #define | XSP3_SOFT_SCALER_RESET_TICKS 1 |
| #define | XSP3_SOFT_SCALER_NUM_RESETS 2 |
| #define | XSP3_SOFT_SCALER_ALL_EVENT 3 |
| #define | XSP3_SOFT_SCALER_PILEUP 4 |
| #define | XSP3_SOFT_SCALER_ALL_GOOD 5 |
| #define | XSP3_SOFT_SCALER_ALL_GOOD_GG 6 |
| | All Good with good grade.
|
| #define | XSP3_SOFT_SCALER_ALL_EVENT_GG 7 |
| | All event with good Grade.
|
| #define | XSP3_SOFT_SCALER_NUM_WINDOWS 2 |
| #define | XSP3_HW_USED_SCALERS 7 |
| #define | XSP3_HW_DEFINED_SCALERS 8 |
| #define | XSP3_ENERGIES 4096 |
| #define | XSP3_MAX_CARDS 8 |
| | Maximum number of cards in a logical system.
|
| #define | XSP3_MAX_CARD_INDEX 62 |
| | Maximum card index across all systems.
|
| #define | XSP3_MAX_PATH 20 |
| #define | XSP3_MAX_IP_CHARS 16 |
| #define | XSP3_MAX_CHANS_PER_CARD 9 |
| #define | XSP3_MAX_MSG_LEN 1024 |
| #define | XSP3_MAX_CHANS (XSP3_MAX_CARDS*XSP3_MAX_CHANS_PER_CARD) |
| #define | XSP3_MAX_ROI 8 |
| #define | XSP3_ADC_RANGE 65536 |
| #define | XSP3_MAX_TOP_SAMPLES 1024 |
| #define | XSP3_TRAILER_LWORDS 2 |
| #define | XSP3_10GTX_SOF 0x80000000 |
| #define | XSP3_10GTX_EOF 0x40000000 |
| #define | XSP3_10GTX_PAD 0x20000000 |
| #define | XSP3_10GTX_PACKET_MASK 0x0FFFFFFF |
| #define | XSP3_10GTX_TIMEOUT 30 |
| #define | XSP3_OK 0 |
| | [XSP3_ERROR_CODES]
|
| #define | XSP3_ERROR -1 |
| #define | XSP3_INVALID_PATH -2 |
| #define | XSP3_ILLEGAL_CARD -3 |
| #define | XSP3_ILLEGAL_SUBPATH -4 |
| #define | XSP3_INVALID_DMA_STREAM -5 |
| #define | XSP3_RANGE_CHECK -6 |
| #define | XSP3_INVALID_SCOPE_MOD -7 |
| #define | XSP3_OUT_OF_MEMORY -8 |
| #define | XSP_MAX_MAC_ADDR 18 |
| | [XSP3_ERROR_CODES]
|
| #define | XSP_MAX_IP_ADDR 16 |
| #define | XSP3_FEATURE_ACK_EOF_NONE 0 |
| | The 3 off 32 bit feature registers store 3 x 8 x 4 bit fields. Unpacked in struct using chars.
|
| #define | XSP3_FEATURE_ACK_EOF_YES 1 |
| | Acknowledge packets with frame number only.
|
| #define | XSP3_FEATURE_ACK_EOF_WITH_TIME 2 |
| | Acknowledge packets also tell total exposure time of frame.
|
| #define | XSP3_REVISION 0 |
| | Revision Number D[31..16] = major revision, D[15..0] = minor revision.
|
| #define | XSP3_REG_PRESENT 1 |
| | Read/Writeable register present Mask bit 0 = Register offset 0.
|
| #define | XSP3_CHAN_CONT 2 |
| | General Chan Control functions.
|
| #define | XSP3_TP_CYCLES 3 |
| | Test pattern generator cycles register when present.
|
| #define | XSP3_RESETA 4 |
| | Reset Control A.
|
| #define | XSP3_RESETB 5 |
| | Reset Control B.
|
| #define | XSP3_RESETC 6 |
| | Reset Control C.
|
| #define | XSP3_GLITCHA 7 |
| | Glitch control A.
|
| #define | XSP3_GLITCHB 8 |
| | Glitch control B.
|
| #define | XSP3_TRIGB_THRES 10 |
| | Individual Trigger B Threshold control.
|
| #define | XSP3_TRIGB_TIMEA 11 |
| | Individual Trigger B TimesA.
|
| #define | XSP3_TRIGB_TIMEB 12 |
| | Individual Trigger B TimesB.
|
| #define | XSP3_TRIGBC_TIME 13 |
| | Individual Trigger B or C OTD servo Times.
|
| #define | XSP3_TRIGC_THRES 14 |
| | Individual Trigger C Threshold and averaging.
|
| #define | XSP3_TRIGB_RINGING 15 |
| | Ringing removal for Trigger B 1st differential.
|
| #define | XSP3_CAL_CONT 16 |
| | Cal Cont.
|
| #define | XSP3_SERVO_CONT_A 17 |
| | Servo Control A.
|
| #define | XSP3_SERVO_CONT_B 18 |
| | Servo Control B.
|
| #define | XSP3_SERVO_CONT_C 19 |
| | Servo Control C.
|
| #define | XSP3_WINDOW0_THRES 24 |
| | Window values for Window 0 Scaler.
|
| #define | XSP3_WINDOW1_THRES 25 |
| | Window values for Window 1 Scaler.
|
| #define | XSP3_GOOD_THRES 26 |
| | Window values for Good Event Scaler.
|
| #define | XSP3_FORMAT 28 |
| | Format Control.
|
| #define | XSP3_SCOPE_SEARCH 29 |
| | Special scope search aid, when configured.
|
| #define | XSP_MAX_NUM_CHAN_REG 32 |
| | Maximum number of writeable channel registers use for initialise.
|
| #define | XSP3_LIVE_TIME_SCAL (32+0) |
| | Total Time Scaler direct readback.
|
| #define | XSP3_RESET_TICKS_SCAL (32+1) |
| | Reset Ticks Scaler direct readback.
|
| #define | XSP3_RESET_COUNT_SCAL (32+2) |
| | Reset Count Scaler direct readback.
|
| #define | XSP3_ALL_EVENT_SCAL (32+3) |
| | All event Scaler direct readback.
|
| #define | XSP3_GOOD_EVENT_SCAL (32+4) |
| | All event Scaler direct readback.
|
| #define | XSP3_IN_WIDNOW0_SCAL (32+5) |
| | All event Scaler direct readback.
|
| #define | XSP3_IN_WIDNOW1_SCAL (32+6) |
| | All event Scaler direct readback.
|
| #define | XSP3_MAX_NUM_READ_CHAN_REG 39 |
| #define | XSP3_REVISION_GET_DETECTOR(x) (((x)>>24)&0xFF) |
| #define | XSP3_REVISION_GET_MAJOR(x) (((x)>>12)&0xFFF) |
| #define | XSP3_REVISION_GET_MINOR(x) ((x)&0xFFF) |
| #define | XSP3_CC_SEL_DATA(x) ((x)&7) |
| | [XSP3_CC_REGISTER]
|
| #define | XSP3_CC_SEL_DATA_NORMAL 0 |
| #define | XSP3_CC_SEL_DATA_ALTERNATE 1 |
| #define | XSP3_CC_SEL_DATA_MUX_DATA 2 |
| #define | XSP3_CC_SEL_DATA_EXT0 4 |
| #define | XSP3_CC_SEL_DATA_EXT1 5 |
| #define | XSP3_CC_DATA_INV (1<<3) |
| | 1's complement the data when adc data ramps from high to low
|
| #define | XSP3_CC_DET_RESET_INV (1<<4) |
| #define | XSP3_CC_USE_TEST_PAT (1<<5) |
| #define | XSP3_CC_TP_CONTINUOUS (1<<6) |
| #define | XSP3_CC_USE_RESET_FROM_DIFF (1<<7) |
| #define | XSP3_CC_GR_MASKS_RESET_TICKS (1<<8) |
| #define | XSP3_CC_GR_FROM_PLAYBACK (1<<9) |
| #define | XSP3_CC_ENB_INL_CORR (1<<10) |
| #define | XSP3_CC_AVE_RINGING_REMOVED (1<<11) |
| #define | XSP3_CC_LIVE_TICKS_MODE(x) (((x)&7)<<12) |
| #define | XSP3_CC_GOOD_GRADE_MODE(x) (((x)&3)<<15) |
| #define | XSP3_CC_NO_EXTEND_RESET_TICKS (1<<17) |
| | Do not extend the reset ticks until any event overlapping the end of reset finishes.
|
| #define | XSP3_CC_RUN_AVE_BY_WIDTH (1<<18) |
| | Enable event lead/tail correction by OTD width.
|
| #define | XSP3_CC_NEB_EVENT_MODE(x) (((x)&7)<<20) |
| #define | XSP3_CC_MAX_FILT_LEN(x) (((x)&7)<<24) |
| #define | XSP3_CC_GET_MAX_FILT_LEN(x) (((x)>>24)&7) |
| #define | XSP3_CC_SEL_ENERGY(x) (((x)&0xF)<<28) |
| #define | XSP3_CC_GET_GOOD_GRADE_MODE(x) (((x)>>15)&3) |
| #define | XSP3_CC_NEB_EVENT_NONE 0 |
| | Disabled.
|
| #define | XSP3_CC_NEB_EVENT_TRIGGER 1 |
| | Trigger channel on neighbour keep all events.
|
| #define | XSP3_CC_NEB_EVENT_REJECT_LONE 2 |
| | Reject lone neighbour events.
|
| #define | XSP3_CC_NEB_EVENT_REJECT_ALL 3 |
| | Reject all neighbour events.
|
| #define | XSP3_CC_SEND_RESET_WIDTHS (1<<12) |
| #define | XSP3_CC_LT_OFF 0 |
| | Live ticks are not counter on scalers.
|
| #define | XSP3_CC_LT_RESET_TICKS 1 |
| | Live ticks are counted on Reset Ticks Counter (cannot compare with standard DTC, but suitable for run modes.
|
| #define | XSP3_CC_LT_IN_WINDOW1 2 |
| | Live ticks are counted in the in-window1 counter. Both DTC techniques can be tried.
|
| #define | XSP3_CC_LT_PILEUP 3 |
| | Live ticks are counted in the pile-up counter. Both DTC techniques can be tried.
|
| #define | XSP3_CC_GOOD_GRADE_MCA_ONLY 0 |
| | Good grade masks MCA only. Scalers unchanged.
|
| #define | XSP3_CC_GOOD_GRADE_MCA_WIN 1 |
| | Good grade masks MCA and inWin scalers. Correct with increased dead time.
|
| #define | XSP3_CC_GOOD_GRADE_ALL_EVENT 2 |
| | Good grade masks MCA and Inwin 0, 1. AllEvent and all good become AllEvent and AllEvent_GoodGrade.
|
| #define | XSP3_CC_GOOD_GRADE_ALL_GOOD 3 |
| | Good grade masks MCA and Inwin 0, 1.
|
| #define | XSP3_RESET_TIME(x) (((x)&0x3ff)<<0) |
| | [XSP3_CC_REGISTER]
|
| #define | XSP3_RESET_OUTPUT_RESET (1<<10) |
| #define | XSP3_RESET_OVER_RANGE_EXTEND (1<<11) |
| #define | XSP3_RESET_DELAY(x) (((x)&0xf)<<12) |
| #define | XSP3_RESET_THRES(x) (((x)&0xFFFF)<<16) |
| #define | XSP3_RESET_GET_TIME(x) (((x)>>0)&0x3ff) |
| #define | XSP3_RESET_GET_DELAY(x) (((x)>>12)&0xf) |
| #define | XSP3_RESET_GET_THRES(x) (((x)>>16)&0xFFFF) |
| #define | XSP3_RESET_MAX_RESET_TIME 0x3FF |
| | [XSP3_RESET_A_REGISTER]
|
| #define | XSP3_RESET_MAX_RESET_THRES 0xFFFF |
| #define | XSP3_RESET_MAX_DIFF_DEL 0xF |
| #define | XSP3_RESET_MAX_DATA_DEL 0x3F |
| #define | XSP3_RESET_MIN_DIFF_THRES (-2048*16) |
| #define | XSP3_RESET_MAX_RAW_TIME 0x3F |
| #define | XSP3_RESET_B_DIFF_DEL(x) (((x)&0xF)<<0) |
| | [XSP3_RESET_B_REGISTER]
|
| #define | XSP3_RESET_B_DATA_DEL(x) (((x)&0x3F)<<4) |
| #define | XSP3_RESET_B_AVE_CONT(x) (((x)&0x3)<<10) |
| #define | XSP3_RESET_B_DIFF_THRES(x) ((((x)>>4)&0x7FF)<<12) |
| #define | XSP3_RESET_B_RAW_TIME(x) (((x)&0x3F)<<23) |
| #define | XSP3_RESET_B_SET_MODE(x) (((x)&0x3)<<30) |
| #define | XSP3_RESET_B_MODE_OFF 0 |
| | [XSP3_RESET_B_REGISTER]
|
| #define | XSP3_RESET_B_MODE_FROM_START 1 |
| #define | XSP3_RESET_B_MODE_END_GRAD 2 |
| #define | XSP3_RESET_B_MODE_END_LEVEL 3 |
| #define | XSP3_RESET_B_SUM1 0 |
| #define | XSP3_RESET_B_SUM2 1 |
| #define | XSP3_RESET_B_SUM4 2 |
| #define | XSP3_RESET_C_THRES_FALL(x) (((x)&0xFFFF)<<16) |
| | [XSP3_RESET_C_REGISTER]
|
| #define | XSP3_RESET_C_THRES_RISE(x) (((x)&0xFFFF)<<0) |
| #define | XSP3_RESET_C_GET_THRES_FALL(x) (((x)>>16)&0xFFFF) |
| #define | XSP3_RESET_C_GET_THRES_RISE(x) ((x)&0xFFFF) |
| #define | XSP3_GLITCH_A_ENABLE (1<<0) |
| | [XSP3_RESET_C_REGISTER]
|
| #define | XSP3_GLITCH_A_GLITCH_TIME(x) (((x)&0x1ff)<<1) |
| #define | XSP3_GLITCH_A_GLITCH_THRES8(x) (((x)&0xff)<<10) |
| #define | XSP3_GLITCH_A_GLITCH_THRES10(x) (((x)&0x3ff)<<10) |
| #define | XSP3_GLITCH_A_DIFF_TIME(x) (((x)&0x1)<<18) |
| #define | XSP3_GLITCH_A_PRE_TIME(x) (((x)&0x1f)<<20) |
| #define | XSP3_GLITCH_A_FROM_GLOBAL_RESET_LEVEL (1<<25) |
| #define | XSP3_GLITCH_A_FROM_GLOBAL_RESET_EDGE (1<<26) |
| #define | XSP3_GLITCH_A_RETRIGGER (1<<27) |
| #define | XSP3_GLITCH_A_MASK_GLITCH_EVENT (1<<28) |
| #define | XSP3_GLITCH_A_COUNT_GLICTH_TIME (1<<29) |
| #define | XSP3_GLITCH_A_EVDET(x) (((x)&0x3)<<30) |
| | From XSPRESS2 trigger-A (2 gradients over threshold). No longer used for this, now in XSP3_GLITCH_A_PRE_TIME_LONG.
|
| #define | XSP3_GLITCH_A_PRE_TIME_LONG(x) (((x)&0x1f)<<20|((x)&0x60)<<25) |
| | Pusedo Log coded Pre time. 0...63 => 0..63 , 64..127 => 0, 8, 16..504.
|
| #define | XSP3_GLITCH_A_GET_GLITCH_TIME(x) (((x)>>1)&0x1ff) |
| | [XSP3_GLITCH_A_REGISTER]
|
| #define | XSP3_GLITCH_A_GET_GLITCH_THRES(x) (((x)>>10)&0xff) |
| #define | XSP3_GLITCH_A_MAX_GLITCH_TIME 0x1FF |
| #define | XSP3_GLITCH_A_MAX_PRE_TIME 0x1F |
| | Maximum pre-time with normal Full Gdet build.
|
| #define | XSP3_GLITCH_A_MAX_PRE_TIME_LONG 0x1FF |
| | Maximum pre-time with BRAM based dealy GDet, see XSP3_FEATURE_GDET_LONG.
|
| #define | XSP3_GLITCH_A_MIN_THRES -255 |
| #define | XSP3_GLITCH_B_HOLDOFF(x) ((x)&0x1FF) |
| | [XSP3_GLITCH_B_REGISTER]
|
| #define | XSP3_GLITCH_B_SUMMODE(x) (((x)&3)<<9) |
| #define | XSP3_GLITCH_B_GET_SUMMODE(x) (((x)>>9)&3) |
| #define | XSP3_GLITCH_B_MASK_BOG_EVENT (1<<11) |
| #define | XSP3_GLITCH_B_GLITCH_STRETCH(x) (((x)&0x3F)<<12) |
| #define | XSP3_GLITCH_B_GET_GLITCH_STRETCH(x) (((x)>>12)&0x3F) |
| #define | XSP3_GLITCH_B_BGE_STRETCH(x) (((x)&0x1F)<<18) |
| #define | XSP3_GLITCH_B_GET_BGE_STRETCH(x) (((x)>>18)&0x1F)) |
| #define | XSP3_GLITCH_B_DIFF_SEP(x) (((x)&0xF)<<24) |
| #define | XSP3_GLITCH_B_GET_DIFF_SEP(x) (((x)>>24)&0xF) |
| #define | XSP3_GLITCH_B_FORCE_EVENT (1<<23) |
| #define | XSP3_GLITCH_B_BGE_EXTEND (1<<28) |
| #define | XSP3_GLITCH_B_SHORT_PADDING (1<<29) |
| #define | XSP3_GLITCH_B_BGE_LOOKAHEAD (1<<30) |
| #define | XSP3_GLITCH_B_SUM1 0 |
| | [XSP3_GLITCH_B_REGISTER]
|
| #define | XSP3_GLITCH_B_SUM2 1 |
| #define | XSP3_GLITCH_B_SUM4 2 |
| #define | XSP3_GLITCH_B_MAX_HOLDOFF 0x1FF |
| #define | XSP3_GLITCH_B_MAX_STRETCH 0x3f |
| #define | XSP3_GLITCH_B_MAX_BGE_STRETCH 0x1f |
| #define | XSP3_GLITCH_B_MAX_DIFF_SEP 15 |
| #define | X3TRIG_B_THRES_SET_ARM(x) (((x)&0x3FF)) |
| | [XSP3_TRIGGERB_THRESHOLD_REGISTER]
|
| #define | X3TRIG_B_THRES_SET_END(x) (((x)&0x3FF)<<10) |
| #define | X3TRIG_B_THRES_SET_REARM(x) (((x)&0x3FF)<<20) |
| #define | X3TRIG_B_THRES_TWO_OVER (1<<30) |
| #define | X3TRIG_B_THRES_ENABLE_CFD (1<<31) |
| #define | X3TRIG_B_THRES_GET_ARM(x) (((x)&0x3FF)) |
| #define | X3TRIG_B_THRES_GET_END(x) (((x)>>10)&0x3FF) |
| #define | X3TRIG_B_THRES_GET_REARM(x) (((x)>>20)&0x3FF) |
| #define | X3TRIG_B_ENABLE_CFD 1 |
| | [XSP3_TRIGGERB_THRESHOLD_REGISTER]
|
| #define | X3TRIG_B_ENABLE_OVERTHR 2 |
| #define | X3TRIG_B_TIME_SET_DIFF1(x) (((x)&0x7f)) |
| | [XSP3_TRIGGERB_TIMEA_REGISTER]
|
| #define | X3TRIG_B_TIME_SET_DIFF2(x) (((x)&0x7f)<<7) |
| #define | X3TRIG_B_TIME_SET_DATA(x) (((x)&0x7f)<<14) |
| #define | X3TRIG_B_TIME_SET_EVENT(x) (((x)&0x7f)<<21) |
| #define | X3TRIG_B_TIME_SET_AVEMODE(x) (((x)&3)<<28) |
| #define | X3TRIG_B_TIME_DISABLE_SPLIT (1<<30) |
| #define | X3TRIG_B_TIME_ENABLE_OVERTHR (1<<31) |
| #define | X3TRIG_B_TIME_GET_DIFF1(x) (((x)&0x7f)) |
| #define | X3TRIG_B_TIME_GET_DIFF2(x) (((x)>>7)&0x7f) |
| #define | X3TRIG_B_TIME_GET_DATA(x) (((x)>>14)&0x7f) |
| #define | X3TRIG_B_TIME_GET_EVENT(x) (((x)>>21)&0x7f) |
| #define | X3TRIG_B_TIME_GET_AVEMODE(x) (((x)>>28)&3) |
| #define | X3TRIG_B_TIME_DIFF_OFFSET_BRAM 3 |
| #define | X3TRIG_B_TIME_DIFF_OFFSET_SRL 1 |
| #define | X3TRIG_B_TIME_DIFF_MAX_BRAM 0x7F |
| #define | X3TRIG_B_TIME_DIFF_MAX_SRL 0x1F |
| #define | X3TRIG_B_TIME_DATA_DELAY_OFFSET 3 |
| #define | X3TRIG_B_MAX_DATA_DEL 0x7F |
| #define | X3TRIG_B_SET_OVERTHR_DELAY(x) (((x)&0x1F)) |
| | [XSP3_TRIGGERB_TIMEA_REGISTER]
|
| #define | X3TRIG_B_SET_OVERTHR_STRETCH(x) (((x)&0x3F)<<8) |
| #define | X3TRIG_B_SET_OVERTHR_TRIM(x) (((x)&0x1F)<<16) |
| #define | X3TRIG_B_GET_OVERTHR_DELAY(x) (((x)&0x1F)) |
| #define | X3TRIG_B_GET_OVERTHR_STRETCH(x) (((x)>>8)&0x3F) |
| #define | X3TRIG_B_GET_OVERTHR_TRIM(x) (((x)>>16)&0x1F) |
| #define | X3TRIG_B_TIMEB_SET_THRES_SCALE(x) (((x)&1)<<30) |
| | [XSP3_TRIGGERB_OVER_THRESHOLD_REGISTER]
|
| #define | X3TRIG_B_TIMEB_SCALED_THRES_MODE (1<<31) |
| #define | X3TRIG_B_TIMEB_GET_THRES_SCALE(x) (((x)>>30)&1) |
| #define | X3TRIG_BC_SET_OVERTHR_SERVO_DELAY(x) (((x)&0x1F)) |
| | [XSP3_TRIGGERB_TIMEB_REGISTER]
|
| #define | X3TRIG_BC_SET_OVERTHR_SERVO_STRETCH(x) (((x)&0x3F)<<8) |
| #define | X3TRIG_BC_GET_OVERTHR_SERVO_DELAY(x) (((x)&0x1F)) |
| #define | X3TRIG_BC_GET_OVERTHR_SERVO_STRETCH(x) (((x)>>8)&0x3F) |
| #define | X3TRIG_BC_OVERTHR_SERVO_USE_DET_RESET (1<<31) |
| #define | X3TRIG_BC_OVERTHR_USE_DET_RESET (1<<30) |
| #define | X3TRIG_C_SET_OVERTHR_SERVO_TRIM(x) (((x)&0xF)<<16) |
| | [XSP3_TRIGGERBC_OVER_THRESHOLD_SERVO_REGISTER]
|
| #define | X3TRIG_C_GET_OVERTHR_SERVO_TRIM(x) (((x)>>16)&0xF) |
| #define | X3TRIG_C_THRES_SET_ARM(x) (((x)&0x3FF)) |
| | [XSP3_TRIGGERC_OVER_THRESHOLD_SERVO_REGISTER]
|
| #define | X3TRIG_C_THRES_SET_END(x) (((x)&0x3FF)<<10) |
| #define | X3TRIG_C_THRES_SET_DIFF1(x) (((x)&0x7F)<<20) |
| #define | X3TRIG_C_THRES_SET_AVEMODE(x) (((x)&3)<<27) |
| #define | X3TRIG_C_THRES_TWO_OVER (1<<29) |
| #define | X3TRIG_C_THRES_ENB_NEGATIVE (1<<30) |
| #define | X3TRIG_C_THRES_IGNORE_NEAR_GLITCH (1<<31) |
| #define | X3TRIG_C_THRES_GET_ARM(x) (((x)&0x3FF)) |
| #define | X3TRIG_C_THRES_GET_END(x) (((x)>>10)&0x3FF) |
| #define | X3TRIG_C_THRES_GET_DIFF1(x) (((x)>>20)&0x7F) |
| #define | X3TRIG_C_THRES_GET_AVEMODE(x) (((x)>>27)&3) |
| #define | X3TRIG_B_RINGING_SCALE_A(x) (((x)&0x7FF)) |
| | [XSP3_TRIGGERC_THRESHOLD_REGISTER]
|
| #define | X3TRIG_B_RINGING_DELAY_A(x) (((x)&0x1F)<<11) |
| #define | X3TRIG_B_RINGING_SCALE_B(x) (((x)&0x7FF)<<16) |
| #define | X3TRIG_B_RINGING_DELAY_B(x) (((x)&0x1F)<<27) |
| #define | X3TRIG_B_GET_RINGING_SCALE_A(x) (((x)&0x7FF)) |
| #define | X3TRIG_B_GET_RINGING_DELAY_A(x) (((x)>>1)&0x1F) |
| #define | X3TRIG_B_GET_RINGING_SCALE_B(x) (((x)>>16)&0x7FF) |
| #define | X3TRIG_B_GET_RINGING_DELAY_B(x) (((x)>>27)&0x1F) |
| #define | XSP3_TRIGB_RING_MIN_DEL 3 |
| #define | X3TRIG_C_AVE2 0 |
| | [XSP3_TRIGGER_B_RINGING_REGISTER]
|
| #define | X3TRIG_C_AVE4 1 |
| #define | X3TRIG_C_AVE8 2 |
| #define | X3TRIG_C_AVE16 3 |
| #define | X3TRIG_B_SCALED_THRES_OFF 0 |
| | [XSP3_TRIGGERC_AVEMODE_BITS 27-28]
|
| #define | X3TRIG_B_SCALED_THRES_DIV4 0x8 |
| #define | X3TRIG_B_SCALED_THRES_DIV2 0x9 |
| #define | X3TRIG_B_AVE1 0 |
| #define | X3TRIG_B_AVE2 1 |
| #define | X3TRIG_B_AVE4 2 |
| #define | X3TRIG_B_AVE8 3 |
| #define | X3DEFAULT_TRIGB_DELAY (40+16) |
| #define | X3TRIG_B_MIN_DELAY (18+8+16+1) |
| #define | X3TRIG_B_MAX_TRIM 31 |
| #define | X3TRIG_B_MAX_OVERTHR_DELAY 31 |
| #define | X3TRIG_B_MAX_OVERTHR_STRETCH 0x3F |
| #define | X3TRIG_B_MAX_THRES 0x3FF |
| #define | X3TRIG_C_MAX_THRES 0x3FF |
| #define | X3TRIG_C_MAX_SEP1 0x7F |
| #define | X3TRIG_C_MAX_OVERTHR_DELAY 31 |
| #define | X3TRIG_C_MAX_OVERTHR_STRETCH 0x3F |
| #define | X3TRIG_C_MAX_TRIM 15 |
| #define | X3TRIG_B_MAX_EVENT_TIMEL 0x7F |
| #define | XSP3_CAL_EV_ENABLE 1 |
| | Enable Calibration events.
|
| #define | XSP3_CAL_EV_PERIOD(x) (((x)&0x3FFF)<<1) |
| | Set period of calibration events. In 100 ns Units.
|
| #define | XSP3_CAL_EV_AVOID (1<<31) |
| | Calibration event avoid clashing with real events.
|
| #define | XSP3_CAL_EV_MAX_PERIOD 0x3FFF |
| | Maximum cal event period in 100 ns Units.
|
| #define | X3WINDOW_LOW_START 0 |
| #define | X3WINDOW_LOW_MASK 0x0000ffff |
| #define | X3WINDOW_HIGH_START 16 |
| #define | X3WINDOW_HIGH_MASK 0xffff0000 |
| #define | X3WINDOW_ALL_EVENT_MASK 0xf000f000 |
| #define | X3SCOPE_DELAY_TRIG (1<<23) |
| #define | X3SCOPE_RESTART_SERVO (1<<24) |
| #define | XSP3_SERVO_C_ENABLE 1 |
| #define | XSP3_SERVO_A_DIV(x) ((x)&7) |
| | [XSP3_SERVO_A_REGISTER]
|
| #define | XSP3_SERVO_A_STRETCH(x) (((x)&0x7F)<<3) |
| #define | XSP3_SERVO_A_PWL_TIME(x) (((x)&3)<<10) |
| #define | XSP3_SERVO_A_PRE_GAP(x) (((x)&0xF)<<12) |
| #define | XSP3_SERVO_A_GRAD_ERR_LIM(x) (((x)&0xFF)<<16) |
| #define | XSP3_SERVO_A_MASK_GLOBAL_GLITCH (1<<24) |
| #define | XSP3_SERVO_A_ACCUM_ON_UPDATE (1<<25) |
| #define | XSP3_SERVO_A_CLEAR_ON_UPDATE (1<<26) |
| #define | XSP3_SERVO_A_CAL_EXCLUDE(x) (((x)&3)<<27) |
| #define | XSP3_SERVO_A_FROM_CAL (1<<29) |
| #define | XSP3_SERVO_A_MASK_GLITCH (1<<30) |
| #define | XSP3_SERVO_A_PWL_ENB (1<<31) |
| #define | XSP3_SERVO_A_GET_STRETCH(x) (((x)>>3)&0x7F) |
| #define | XSP3_SERVO_A_GET_PWL_TIME(x) (((x)>>10)&3) |
| #define | XSP3_SERVO_A_GET_PRE_GAP(x) (((x)>>12)&0xF) |
| #define | XSP3_SERVO_B_GRAD_EST_LIM(x) (((x)&0xFFFF)<<0) |
| | [XSP3_SERVO_A_REGISTER]
|
| #define | XSP3_SERVO_B_ENB_GLOB_GRAD (1<<16) |
| #define | XSP3_SERVO_B_GLOB_ADJ_SIZE(x) (((x)&0x3)<<17) |
| #define | XSP3_SERVO_B_GLOB_ADJ_POSN(x) (((x)&0x7F)<<19) |
| #define | XSP3_SERVO_B_GLOB_ADJ_SHIFT(x) (((x)&0x7)<<26) |
| #define | XSP3_SERVO_B_STRETCH_TIME (1<<29) |
| #define | XSP3_SERVO_B_GLITCH_AS_RESET (1<<30) |
| #define | XSP3_SERVO_B_USE_ADC_TOP4 (1<<31) |
| #define | XSP3_SERVO_C_ENB_SERVO (1<<0) |
| | [XSP3_SERVO_B_REGISTER]
|
| #define | XSP3_SERVO_C_RESTART_ON_RUN (1<<1) |
| #define | XSP3_SERVO_C_USE_OTD_SERVO (1<<2) |
| #define | XSP3_SERVO_C_SET_RESET_STRETCH(x) (((x)&0x1FF)<<3) |
| #define | XSP3_SERVO_C_SET_DITHER_CONT(x) (((x)&0x7)<<12) |
| #define | XSP3_SERVO_C_GET_RESET_STRETCH(x) (((x)>>3)&0x1FF) |
| #define | XSP3_SERVO_C_GET_DITHER_CONT(x) (((x)>>12)&0x7) |
| #define | XSP3_SERVO_C_MAX_RESET_STRETCH 0x1FF |
| #define | XSP3_SERVO_C_MAX_DITHER_CONT 5 |
| #define | XSP3_SERVO_C_ENB_BI_LIN_TIME (1<<15) |
| | Enable detailed control of Bi-linear timing.
|
| #define | XSP3_SERVO_C_BI_LIN_TIME_CODE(x) (((x)&3)<<16) |
| | Coded length for longer chunks 0=> 128, 1=>256, 2=>512, 3=>1024.
|
| #define | XSP3_SERVO_C_BI_LIN_TIME_START(x) (((x)&7)<<18) |
| | Coded number of short chunks before jumping to longer chunks. 0=>4, 1=>8, 2=>16, 3=>32, 4=>64, 5=>128, 6=>256, 7=>256.
|
| #define | XSP3_SERVO_MAX_ERR_LIM 0xFF |
| | [XSP3_SERVO_C_REGISTER]
|
| #define | XSP3_SERVO_MAX_STRETCH 0x7F |
| #define | XSP3_CHAN_GLOB 15 |
| #define | XSP3_REGION_RAM_TESTPAT 1 |
| | [XSP3_REGIONS]
|
| #define | XSP3_REGION_RAM_RESET_TAIL 2 |
| #define | XSP3_REGION_RAM_QUOTIENT 3 |
| #define | XSP3_REGION_RAM_ROI 4 |
| #define | XSP3_REGION_RAM_EVENT_TAIL 5 |
| #define | XSP3_REGION_RAM_PWL_SERVO 6 |
| #define | XSP3_REGION_RAM_PILEUP_TIME 7 |
| #define | XSP3_REGION_RAM_AUX1 8 |
| #define | XSP3_REGION_RAM_SERVO_TAIL 9 |
| #define | XSP3_REGION_RAM_EVENT_LEAD 10 |
| #define | XSP3_REGION_GLOB_REG 15 |
| #define | XSP3_REGION_RAM_MAX 10 |
| | [XSP3_REGIONS]
|
| #define | XSP3_REGION_REGS 0 |
| #define | XSP3_REGS_SIZE 32 |
| #define | XSP3_CHAN_TP_SIZE 0 |
| #define | XSP3_RESET_TAIL_SIZE 1024 |
| #define | XSP3_QUOTIENT_SIZE 1024 |
| #define | XSP3_ROI_SIZE 4096 |
| #define | XSP3_EVENT_TAIL_SIZE 1024 |
| #define | XSP3_PWL_SERVO_SIZE 512 |
| #define | XSP3_PILEUP_TIME_SIZE 2048 |
| #define | XSP3_AUX1_SIZE 4096 |
| #define | XSP3_SERVO_TAIL_SIZE 1024 |
| #define | XSP3_EVENT_LEAD_SIZE 1024 |
| #define | XSP3_EVENT_TAIL_W4_NT 512 |
| #define | XSP3_EVENT_TAIL_W4_NW 16 |
| #define | XSP3_EVENT_LEAD_W4_NT 512 |
| #define | XSP3_EVENT_LEAD_W4_NW 16 |
| #define | XSP3_EVENT_LEAD_TAIL_MAX_NT 16 |
| #define | XSP3_MAX_BRAM_SIZE 8192 |
| #define | XSP3_FEV_TP_RESET 0x8000 |
| #define | XSP3_PWL_SERVO_SIZE16 2048 |
| #define | XSP3_GLOB_CLOCK_CONT 0 |
| #define | XSP3_GLOB_MDIO_WRITE 1 |
| #define | XSP3_GLOB_TIMING_A 2 |
| #define | XSP3_GLOB_TIMING_FIXED 3 |
| #define | XSP3_GLOB_SCOPE_CHAN_SEL 4 |
| #define | XSP3_GLOB_SCOPE_SRC_SEL 5 |
| #define | XSP3_GLOB_SCOPE_NWORDS 6 |
| #define | XSP3_GLOB_SCOPE_ALTERNATE 7 |
| #define | XSP3_GLOB_DATA_PATH_CONT 8 |
| #define | XSP3_GLOB_DATA_MUX_CONT 10 |
| #define | XSP3_NUM_GLOB_REG 15 |
| #define | XSP3_GLOB_ITFG_FRAME_LEN 11 |
| #define | XSP3_GLOB_ITFG_NUM_FRAMES 12 |
| #define | XSP3_GLOB_GLOB_RST_GEN_A 13 |
| #define | XSP3_GLOB_GLOB_RST_GEN_B 14 |
| #define | XSP3_GLOB_FAN_SPEED 31 |
| #define | XSP3_GLOB_MDIO_READ 33 |
| #define | XSP3_GLOB_LL_STATUS 32 |
| #define | XSP3_GLOB_TIMING_STATUS_A 34 |
| #define | XSP3_GLOB_FEATURES_A 37 |
| #define | XSP3_FEATURES_NUM 3 |
| #define | XSP3_GLOB_CLK_FROM_ADC (1<<0) |
| #define | XSP3_GLOB_CLK_SP_RESET (1<<1) |
| #define | XSP3_GLOB_CLK_TP_ENB_SP_TOP (1<<8) |
| #define | XSP3_GLOB_CLK_RS232_SEL (1<<31) |
| #define | XSP3_GTIMA_SRC_FIXED 0 |
| | [XSP3_GLOBAL_CLOCK]
|
| #define | XSP3_GTIMA_SRC_SOFTWARE 0 |
| | Timing controlled by software, incrementing on each subsequent continue.
|
| #define | XSP3_GTIMA_SRC_INTERNAL 1 |
| | Time frame from internal timing generator (for future expansion).
|
| #define | XSP3_GTIMA_SRC_IDC 3 |
| | Time frame incremented and rest by signals from IDC expansion connector.
|
| #define | XSP3_GTIMA_SRC_TTL_VETO_ONLY 4 |
| | Time frame incremented by TTL Input 1.
|
| #define | XSP3_GTIMA_SRC_TTL_BOTH 5 |
| | Time frame incremented by TTL Input 1 and reset to Fixed register by TTL Input 0.
|
| #define | XSP3_GTIMA_SRC_LVDS_VETO_ONLY 6 |
| | Time frame incremented by LVDS Input.
|
| #define | XSP3_GTIMA_SRC_LVDS_BOTH 7 |
| | Time frame incremented and reset by LVDS Inputs.
|
| #define | XSP3_GLOB_TIMA_TF_SRC(x) ((x)&7) |
| | [XSP3_GLOBAL_TIMEA_BITS 0..2]
|
| #define | XSP3_GLOB_TIMA_F0_INV (1<<3) |
| | Invert Frame Zero signal polarity to make signal active low, resets time frame when sampled low by leading edge of Veto.
|
| #define | XSP3_GLOB_TIMA_VETO_INV (1<<4) |
| | Invert Veto signal polarity to make signal active low, counts when Veto input is low.
|
| #define | XSP3_GLOB_TIMA_ENB_SCALER (1<<5) |
| | Enables scalers.
|
| #define | XSP3_GLOB_TIMA_ENB_HIST (1<<6) |
| | Enables histogramming.
|
| #define | XSP3_GLOB_TIMA_LOOP_IO (1<<7) |
| | Loop TTL_IN(0..3) to TTL_OUT(0..3) for hardware testing (only).
|
| #define | XSP3_GLOB_TIMA_NUM_SCAL_CHAN(x) (((x)&0xF)<<8) |
| | Sets the number of channels of scalers to be transfered to memory by the DMA per time frame.
|
| #define | XSP3_GLOB_TIMA_DEBOUNCE(x) (((x)&0xFF)<<16) |
| | Set debounce time in 80 MHz cycles to ignore glitches or ringing on Frame0 or Framign signal from any source.
|
| #define | XSP3_GLOB_TIMA_ALT_TTL(x) (((x)&0xF)<<24) |
| | Alternate uses of the TTL Outputs (including channel in windows signals etc).
|
| #define | XSP3_GLOB_TIMA_RUN (1<<31) |
| | Overall Run enable signal, set after all DMA channels have been configured.
|
| #define | XSP3_GLOB_TIMA_PB_RST (1<<30) |
| | Resets Playback FIFO as part of clean start.
|
| #define | XSP3_GLOB_TIMA_COUNT_ENB (1<<29) |
| | In software timing (XSP3_GTIMA_SRC_FIXED) mode enable counting when high. Transfers scalers on falling edge. After first frame, increments time frame on risign edge.
|
| #define | XSP3_GLOB_TIMA_ITFG_RUN (1<<28) |
| | From versions 11/8/2014 onwards this is a separate Run signal to the internal time frame generator, which could be used to crsh stop the ITFG before stopping the rest.
|
| #define | XSP3_ALT_TTL_TIMING_VETO 0 |
| | [XSP3_GLOBAL_TIMEA_REGISTER]
|
| #define | XSP3_ALT_TTL_TIMING_ALL 1 |
| | Output TTL_OUT(0)= Veto, (1)=Veto (2) = Running, (3) = Paused from Internal TFG (when present).
|
| #define | XSP3_ALT_TTL_TIMING_VETO_GR 4 |
| | Output Global Reset on TTL_OUT(0) and the currently selected Count Enable Signal from Internal TFG or other inputs and replicate 4 times on TTL_OUT 1...3 Rev 1.26 onwards.
|
| #define | XSP3_ALT_TTL_TIMING_ALL_GR 5 |
| | Output Global Reset on TTL_OUT(0) and TTL_OUT(1)=Veto, (2) = Running, (3) = Paused from Internal TFG (when present).
|
| #define | XSP3_ALT_TTL_INWINDOW 0x8 |
| | Output in-window signal for channels 0:3.
|
| #define | XSP3_ALT_TTL_INWINLIVE 0x9 |
| | Output 2 in-window signals and 2 live signals.
|
| #define | XSP3_ALT_TTL_INWINLIVETOGGLE 0xA |
| | Output 2 in-window signals and 2 live signals toggling.
|
| #define | XSP3_ALT_TTL_INWINGOODLIVE 0xB |
| | Outputs in-window Allevent AllGood and LiveLevel from Chan 0.
|
| #define | XSP3_ALT_TTL_INWINGOODLIVETOGGLE 0xC |
| | Outputs in-window Allevent AllGood and Live toggling from Chan 0.
|
| #define | XSP3_GSCOPE_CS_ENB_SCOPE 1 |
| | [XSP3_GLOBAL_TIMEA_ALT_TTL]
|
| #define | XSP3_GSCOPE_CS_BYTE_SWAP (1<<1) |
| #define | XSP3_GSCOPE_CS_DELAY_START (1<<2) |
| #define | XSP3_GSCOPE_CS_EXTRA_DELAY (1<<3) |
| #define | XSP3_GSCOPE_CHAN_SEL(s, x) (((x)&0xF)<<4*((s)+1)) |
| #define | XSP3_GSCOPE_CHAN_SEL_GET(s, x) (((x)>>4*((s)+1))&0xF) |
| #define | XSP3_GSCOPE_CHAN_SEL0(x) (((x)&0xF)<<4) |
| #define | XSP3_GSCOPE_CHAN_SEL1(x) (((x)&0xF)<<8) |
| #define | XSP3_GSCOPE_CHAN_SEL2(x) (((x)&0xF)<<12) |
| #define | XSP3_GSCOPE_CHAN_SEL3(x) (((x)&0xF)<<16) |
| #define | XSP3_GSCOPE_CHAN_SEL4(x) (((x)&0xF)<<20) |
| #define | XSP3_GSCOPE_CHAN_SEL5(x) (((x)&0xF)<<24) |
| #define | XSP3_GSCOPE_SRC_SEL(s, x) (((x)&0xF)<<4*(s)) |
| #define | XSP3_GSCOPE_SRC_SEL_GET(s, x) (((x)>>4*((s)))&0xF) |
| #define | XSP3_GSCOPE_SRC_SEL0(x) (((x)&0xF)<<0) |
| #define | XSP3_GSCOPE_SRC_SEL1(x) (((x)&0xF)<<4) |
| #define | XSP3_GSCOPE_SRC_SEL2(x) (((x)&0xF)<<8) |
| #define | XSP3_GSCOPE_SRC_SEL3(x) (((x)&0xF)<<12) |
| #define | XSP3_GSCOPE_SRC_SEL4(x) (((x)&0xF)<<16) |
| #define | XSP3_GSCOPE_SRC_SEL5(x) (((x)&0xF)<<20) |
| #define | XSP3_GSCOPE_ALT(s, x) (((x)&0xF)<<4*(s)) |
| #define | XSP3_GSCOPE_ALT0(x) (((x)&0xF)<<0) |
| #define | XSP3_GSCOPE_ALT1(x) (((x)&0xF)<<4) |
| #define | XSP3_GSCOPE_ALT2(x) (((x)&0xF)<<8) |
| #define | XSP3_GSCOPE_ALT3(x) (((x)&0xF)<<12) |
| #define | XSP3_GSCOPE_ALT4(x) (((x)&0xF)<<16) |
| #define | XSP3_GSCOPE_ALT5(x) (((x)&0xF)<<20) |
| #define | XSP3_GSCOPE_ALTERNATE_GET(s, x) (((x)>>4*((s)))&0xF) |
| #define | XSP3_SCOPE_NUM_STREAMS 6 |
| #define | XSP3_SCOPE_SEL0_INP 0 |
| | [XSP3_SCOPE_SOURCES]
|
| #define | XSP3_SCOPE_SEL0_DIGITAL 1 |
| #define | XSP3_SCOPE_SEL0_ALL_RESETS 2 |
| #define | XSP3_SCOPE_SEL0_RESET_DET_RESETS 3 |
| #define | XSP3_SCOPE_SEL123_INP 0 |
| #define | XSP3_SCOPE_SEL123_TRIG_B_OUT 1 |
| #define | XSP3_SCOPE_SEL123_SERVO_OUT 2 |
| #define | XSP3_SCOPE_SEL123_DIG_OUT 3 |
| #define | XSP3_SCOPE_SEL45_INP 0 |
| #define | XSP3_SCOPE_SEL45_TRIG_B_OUT 1 |
| #define | XSP3_SCOPE_SEL45_SERVO_OUT 2 |
| #define | XSP3_SCOPE_SEL45_GLITCH 3 |
| #define | XSP3_SCOPE_SEL45_TRIG_B_DIFF1 4 |
| #define | XSP3_SCOPE_SEL45_TRIG_B_DIFF2 5 |
| #define | XSP3_SCOPE_SEL45_SERVO_GRAD_ERR 6 |
| #define | XSP3_SCOPE_SEL45_SERVO_GRAD_EST 7 |
| #define | XSP3_SCOPE_SEL45_RESET_DET 8 |
| #define | XSP3_SCOPE_SEL45_TRIG_C_DIFF1 9 |
| #define | XSP3_GSCOPE_CS_HIST_TO_DMA (1<<2) |
| | [XSP3_SCOPE_SOURCES]
|
| #define | XSP3_DPC_HIST_TO_DMA (1<<0) |
| #define | XSP3_DPC_ENB_10G_RX (1<<1) |
| #define | XSP3_DPC_ENB_10G_RX_ACKS (1<<2) |
| #define | XSP3_DPC_SEL_10G_TX_DMA (1<<3) |
| #define | XSP3_DPC_FARM_MODE (1<<4) |
| #define | XSP3_DPC_RX_RESET (1<<30) |
| #define | XSP3_DPC_TX_RESET (1<<31) |
| #define | XSP3_GLOB_LL_STAT_PLAYBACK_OR (1<<0) |
| #define | XSP3_GLOB_LL_STAT_SCOPE_OR (1<<1) |
| #define | XSP3_GLOB_LL_STAT_SCALERS_OR (1<<2) |
| #define | XLLDMA_SR_IRQ_ON_END_MASK 0x00000040 |
| | IRQ on end has occurred.
|
| #define | XLLDMA_SR_STOP_ON_END_MASK 0x00000020 |
| | Stop on end has occurred.
|
| #define | XLLDMA_SR_COMPLETED_MASK 0x00000010 |
| | BD completed.
|
| #define | XLLDMA_SR_SOP_MASK 0x00000008 |
| | Current BD has SOP set.
|
| #define | XLLDMA_SR_EOP_MASK 0x00000004 |
| | Current BD has EOP set.
|
| #define | XLLDMA_SR_ENGINE_BUSY_MASK 0x00000002 |
| | Channel is busy.
|
| #define | XSP3_GLOB_ADC_MUX(adc) (((adc)&0xF)<<0) |
| | [XSP3_GLOB_ADC_DATA_MUX_CONT]
|
| #define | XSP3_GLOB_TSTAT_A_FRAME(x) (((x)>>0)&0xFFFFFF) |
| | [XSP3_GLOB_ADC_DATA_MUX_CONT]
|
| #define | XSP3_GLOB_TSTAT_A_ITFG_COUNTING(x) (((x)>>24)&0x1) |
| | Read whether the ITFG is currently enabling counting.
|
| #define | XSP3_GLOB_TSTAT_A_ITFG_RUNNING(x) (((x)>>25)&0x1) |
| | Read whether the ITFG is currently running.
|
| #define | XSP3_GLOB_TSTAT_A_ITFG_PAUSED(x) (((x)>>26)&0x1) |
| | Read whether the ITFG is paused wait for software or hardware trigger.
|
| #define | XSP3_GLOB_TSTAT_A_ITFG_FINISHED(x) (((x)>>27)&0x1) |
| | Read whether the ITFG has finished a run. This clears when the bit XSP3_GLOB_TIMA_RUN is negated using xsp3_histogram_stop().
|
| #define | XSP3_GLOB_RST_GEN_A_ENB (1<<0) |
| | Enable Global reset generator.
|
| #define | XSP3_GLOB_RST_GEN_A_SYNC_MODE(x) (((x)&3)<<1) |
| | 0 => Drive Global reset as soon as requested. 1 => Syncronise global reset to beam using TTL_IN(3)
|
| #define | XSP3_GLOB_RST_GEN_A_DET_RESET_WIDTH(x) (((x)&0x7F)<<4) |
| | Width in ADC clock cycles (80 MHz) of detector reset signal sent to the detector.
|
| #define | XSP3_GLOB_RST_GEN_A_HOLD_OFF_TIME(x) (((x)&0x3FF)<<12) |
| | Hold off time in ADC clock cycles from END of detector reset pulse until next cheching for global reset request.
|
| #define | XSP3_GLOB_RST_GEN_A_ACTIVE_DELAY(x) (((x)&0x7F)<<22) |
| | Delay from Det reset to detector asserted to Global Reset Active sent to all cards. (can be 0).
|
| #define | XSP3_GLOB_RST_GEN_B_ACTIVE_WIDTH(x) (((x)&0x3FF)<<0) |
| | Width of Global reset Active signal sent to all cards.
|
| #define | XSP3_GLOB_RST_GEN_B_CIRC_OFFSET(x) (((x)&0x7FF)<<12) |
| | Delay from beam circulation trigger to Detector Reset assertion.
|
| #define | XSP3_GLOB_RST_GEN_MAX_RESET_WIDTH 0x7f |
| #define | XSP3_GLOB_RST_GEN_MAX_HOLD_OFF 0x3ff |
| #define | XSP3_GLOB_RST_GEN_MAX_ACTIVE_DELAY 0x7f |
| #define | XSP3_GLOB_RST_GEN_MAX_ACTIVE_WIDTH 0x3ff |
| #define | XSP3_GLOB_RST_GEN_MAX_CIRC_OFFSET 0x7FF |
| #define | XSP3_RUN_FLAGS_PLAYBACK 1 |
| | [XSP3_RUN_FLAGS]
|
| #define | XSP3_RUN_FLAGS_SCOPE 2 |
| #define | XSP3_RUN_FLAGS_SCALERS 4 |
| #define | XSP3_RUN_FLAGS_HIST 8 |
| #define | XSP3_MT_DISABLE_SCOPE 1 |
| | Disable Thread per card code in xsp3_read_scope_data().
|
| #define | XSP3_MT_DISABLE_MEASURE_TRIG 2 |
| | Disable Thread per card code in measure trigger b code ??
|
| #define | XSP3_SPI_S3_READ_WRITE_MASK 0xFFFFFF |
| #define | XSP3_SPI_SS_SPARTAN 5 |
| #define | XSP3_SPI_SS_CLK0 0 |
| #define | XSP3_SPI_SS_CLK1 1 |
| #define | XSP3_SPI_SS_CLK2 2 |
| #define | XSP3_SPI_SS_CLK3 3 |
| #define | XSP3_SPI_CLK_GOE0 (1<<0) |
| | [XSP3_SPI_REGISTER]
|
| #define | XSP3_SPI_CLK_GOE1 (1<<1) |
| #define | XSP3_SPI_CLK_GOE2 (1<<2) |
| #define | XSP3_SPI_CLK_GOE3 (1<<3) |
| #define | XSP3_SPI_CLK_NSYNC0 (1<<4) |
| #define | XSP3_SPI_CLK_NSYNC1 (1<<5) |
| #define | XSP3_SPI_CLK_NSYNC2 (1<<6) |
| #define | XSP3_SPI_CLK_NSYNC3 (1<<7) |
| #define | XSP3_SPI_DITHER (1<<8) |
| #define | XSP3_SPI_PSU(x) (((x)&0x7F)<<9) |
| #define | XSP3_SPI_TP_TYPE(x) (((x)&0x3)<<21) |
| #define | XSP3_SPI_TP_ENB (1<<23) |
| #define | XSP3_SPI_CLK_LD2 (1<<24) |
| #define | XSP3_SPI_CLK_LD3 (1<<25) |
| #define | XSP3_SPI_CLK_DIS_OVER_TEMP (1<<9) |
| #define | XSP3_SPI_CLK_SHUTDOWN0 (1<<10) |
| #define | XSP3_SPI_CLK_SHUTDOWN123 (1<<11) |
| #define | XSP3_SPI_CLK_SHUTDOWN4 (1<<12) |
| #define | XSP3_SPI_CLK_SHUTDOWN5678 (1<<13) |
| #define | XSP3_I2C_BUS_ADC 3 |
| | [XSP3_SPI_REGISTER]
|
| #define | XSP3_LM75_ADDR(dev) (0x9<<3|((dev)&7)) |
| #define | XSP3_CLK_SRC_INT 0 |
| | [XSP3_CLOCK_SRC]
|
| #define | XSP3_CLK_SRC_XTAL 1 |
| #define | XSP3_CLK_SRC_EXT 2 |
| #define | XSP3_CLK_SRC_FPGA 3 |
| #define | XSP3_CLK_FLAGS_MASTER (1<<0) |
| | [XSP3_CLOCK_SRC]
|
| #define | XSP3_CLK_FLAGS_NO_DITHER (1<<1) |
| #define | XSP3_CLK_FLAGS_STAGE1_ONLY (1<<2) |
| #define | XSP3_CLK_FLAGS_NO_CHECK (1<<3) |
| #define | XSP3_CLK_FLAGS_TP_ENB (1<<4) |
| #define | XSP3_CLK_FLAGS_DIS_OVER_TEMP (1<<5) |
| #define | XSP3_CLK_FLAGS_SHUTDOWN0 (1<<6) |
| #define | XSP3_CLK_FLAGS_SHUTDOWN123 (1<<7) |
| #define | XSP3_CLK_FLAGS_SHUTDOWN4 (1<<8) |
| #define | XSP3_CLK_FLAGS_SHUTDOWN5678 (1<<9) |
| #define | XSP3_FORMAT_PILEUP_REJECT (1<<31) |
| | [XSP3_CLOCK_FLAGS]
|
| #define | XSP3_FORMAT_AUX1_MODE(x) (((x)&0xF)<<4) |
| | [XSP3_FORMAT_LAYOUT]
|
| #define | XSP3_FORMAT_AUX1_THRES(x) (((x)&0x3FF)<<8) |
| #define | XSP3_FORMAT_NBITS_ENG(x) (((x)&0xF)<<21) |
| #define | XSP3_FORMAT_NBITS_ADC(x) (((x)&0x7)<<25) |
| #define | XSP3_FORMAT_AUX_MODE(x) (((x)&0x7)<<28) |
| #define | XSP3_FORMAT_NBITS_AUX0 0 |
| #define | XSP3_FORMAT_NBITS_AUX4 1 |
| #define | XSP3_FORMAT_NBITS_AUX6 2 |
| #define | XSP3_FORMAT_NBITS_AUX8 3 |
| #define | XSP3_FORMAT_NBITS_AUX10 4 |
| #define | XSP3_FORMAT_NBITS_AUX12 5 |
| #define | XSP3_FORMAT_NBITS_AUX14 6 |
| #define | XSP3_FORMAT_NBITS_AUX16 7 |
| #define | XSP3_FORMAT_AUX2_ADC 0 |
| | [XSP3_AUX2_MODE]
|
| #define | XSP3_FORMAT_AUX2_WIDTH 1 |
| #define | XSP3_FORMAT_AUX2_RST_START_ADC 2 |
| #define | XSP3_FORMAT_AUX2_NEB_RST_ADC 3 |
| #define | XSP3_FORMAT_AUX2_NEB_RST_RST_START_ADC 4 |
| #define | XSP3_FORMAT_AUX2_TIME_FROM_RST 5 |
| #define | XSP3_FORMAT_AUX2_NEB_RST_TIME_FROM_RST 6 |
| #define | XSP3_FORMAT_AUX2_NEB_RST_TIME_FROM_RSTX8 7 |
| #define | XSP3_FORMAT_AUX1_MODE_NONE 0 |
| | [XSP3_AUX2_MODE]
|
| #define | XSP3_FORMAT_AUX1_MODE_PILEUP 7 |
| | 1 bit of Aux1, set when pileup detected for Width or hardware
|
| #define | XSP3_FORMAT_AUX1_MODE_GOOD_GRADE 15 |
| | 0 bits, but Masks MCA (and scalers) for events with min < thres
|
| #define | XSP3_FORMAT_RES_MODE_NONE 0 |
| | [XSP3_AUX1_MODE]
|
| #define | XSP3_FORMAT_RES_MODE_MINDIV8 1 |
| #define | XSP3_FORMAT_RES_MODE_THRES 2 |
| #define | XSP3_FORMAT_RES_MODE_LOG 3 |
| #define | XSP3_FORMAT_RES_MODE_TOP 4 |
| #define | XSP3_FORMAT_RES_MODE_BOT 5 |
| #define | XSP3_FORMAT_RES_MODE_MIN 6 |
| #define | XSP3_FORMAT_RES_MODE_PILEUP 7 |
| #define | XSP3_FORMAT_RES_MODE_LUT_SETUP 8 |
| #define | XSP3_FORMAT_RES_MODE_LUT_THRES 9 |
| #define | XSP3_FORMAT_RES_MODE_GOOD_GRADE 15 |
| #define | XSP3_FORMAT_GET_AUX1_MODE(x) (((x)>>4)&0xF) |
| #define | XSP3_FORMAT_GET_AUX1_THRES(x) (((x)>>8)&0x3FF) |
| #define | XSP3_FORMAT_GET_NBITS_ENG_LOST(x) (((x)>>21)&0xF) |
| #define | XSP3_FORMAT_GET_NBITS_ADC(x) (((x)>>25)&0x7) |
| #define | XSP3_MIN_BITS_ENG 1 |
| #define | XSP3_MAX_BITS_ENG 12 |
| #define | XSP3_DTC_OMIT_CHANNEL (1<<0) |
| #define | XSP3_DTC_USE_GOOD_EVENT (1<<1) |
| #define | XSP3_SCALER_TIME 0 |
| #define | XSP3_SCALER_RESETTICKS 1 |
| #define | XSP3_SCALER_RESETCOUNT 2 |
| #define | XSP3_SCALER_ALLEVENT 3 |
| #define | XSP3_SCALER_ALLGOOD 4 |
| #define | XSP3_SCALER_INWINDOW0 5 |
| #define | XSP3_SCALER_INWINDOW1 6 |
| #define | XSP3_SCALER_PILEUP 7 |
| #define | XSP3_MDIO_DIRECT 0 |
| #define | XSP3_MDIO_AUX 1 |
| #define | XSP3_FAN_LOG_POINTS 10000 |
| #define | XSP3_FAN_MODE_OFF 0 |
| #define | XSP3_FAN_MODE_MONITOR_LOOP 1 |
| #define | XSP3_FAN_MODE_MONITOR_ONESHOT 2 |
| #define | XSP3_FAN_MODE_CONTROL 3 |
| #define | XSP3_FAN_CONT_NUM_AVERAGE 10 |
| #define | XSP3_FAN_CONT_FRAC_PRECISION 10 |
| #define | XSP3_FAN_OFFSET_MODE 0 |
| #define | XSP3_FAN_OFFSET_START 1 |
| #define | XSP3_FAN_OFFSET_TEMP 2 |
| #define | XSP3_FAN_OFFSET_MAX 6 |
| #define | XSP3_FAN_OFFSET_SET_POINT 7 |
| #define | XSP3_FAN_OFFSET_P_CONST 8 |
| #define | XSP3_FAN_OFFSET_I_CONST 9 |
| #define | XSP3_FAN_OFFSET_CUR_POINT 10 |
| #define | XSP3_FAN_OFFSET_LOG 11 |
| #define | XSP3_FEATURE_GET_TEST_DATA_SOURCE(x) (((x)>>0)&0xF) |
| #define | XSP3_FEATURE_GET_REAL_DATA_SOURCE(x) (((x)>>4)&0xF) |
| #define | XSP3_FEATURE_GET_DATA_MUX(x) (((x)>>8)&0xF) |
| #define | XSP3_FEATURE_GET_INL_CORR(x) (((x)>>12)&0xF) |
| #define | XSP3_FEATURE_GET_RESET_DETECTOR(x) (((x)>>16)&0xF) |
| #define | XSP3_FEATURE_GET_RESET_CORR(x) (((x)>>20)&0xF) |
| #define | XSP3_FEATURE_GET_GLITCH_DETECT(x) (((x)>>24)&0xF) |
| #define | XSP3_FEATURE_GET_GLITCH_PAD(x) (((x)>>28)&0xF) |
| #define | XSP3_FEATURE_GET_TRIGGER_B(x) (((x)>>0)&0xF) |
| #define | XSP3_FEATURE_GET_TRIGGER_C(x) (((x)>>4)&0xF) |
| #define | XSP3_FEATURE_GET_TRIGGER_EXTRA(x) (((x)>>8)&0xF) |
| #define | XSP3_FEATURE_GET_CALIBRATOR(x) (((x)>>12)&0xF) |
| #define | XSP3_FEATURE_GET_NEIGHBOUR_EVENTS(x) (((x)>>16)&0xF) |
| #define | XSP3_FEATURE_GET_SERVO_BASE(x) (((x)>>20)&0xF) |
| #define | XSP3_FEATURE_GET_SERVO_DETAIL(x) (((x)>>24)&0xF) |
| #define | XSP3_FEATURE_GET_RUN_AVE(x) (((x)>>28)&0xF) |
| #define | XSP3_FEATURE_GET_LEAD_TAIL_CORR(x) (((x)>>0)&0xF) |
| #define | XSP3_FEATURE_GET_OUTPUT_FORMAT(x) (((x)>>4)&0xF) |
| #define | XSP3_FEATURE_GET_FORMAT_DETAILS_A(x) (((x)>>8)&0xF) |
| #define | XSP3_FEATURE_GET_FORMAT_DETAILS_B(x) (((x)>>12)&0xF) |
| #define | XSP3_FEATURE_GET_GLOBAL_RESET(x) (((x)>>16)&0xF) |
| #define | XSP3_FEATURE_GET_TIMING_SOURCE(x) (((x)>>20)&0xF) |
| #define | XSP3_FEATURE_GET_TIMING_GENERATOR(x) (((x)>>24)&0xF) |
| #define | XSP3_FEATURE_GET_SCOPE(x) (((x)>>28)&0xF) |
| #define | XSP3_FEATURE_GET_TEST_SRC_A(x) (((x)>>0)&3) |
| | Test source A from lower 2 bits.
|
| #define | XSP3_FEATURE_GET_TEST_SRC_B(x) (((x)>>2)&3) |
| | Test source A from upper 2 bits.
|
| #define | XSP3_FEATURE_TEST_SRC_A_NONE 0 |
| | No Playback.
|
| #define | XSP3_FEATURE_TEST_SRC_A_PB2 1 |
| | Output is list of complete 32 address offsets for histogramming.
|
| #define | XSP3_FEATURE_TEST_SRC_B_NONE 0 |
| | No test pattern generator (current builds).
|
| #define | XSP3_FEATURE_TEST_SRC_B_TPGEN 1 |
| | BRAM based TP generator.
|
| #define | XSP3_FEATURE_RESET_CORR_FIXED1024 0 |
| | Only build is fixed 1024 point table.
|
| #define | XSP3_FEATURE_GDET_NONE 0 |
| | No glitch detector.
|
| #define | XSP3_FEATURE_GDET_THRES8 1 |
| | Glitch detector from gradient, original 8 bit threshold register layout.
|
| #define | XSP3_FEATURE_GDET_THRES10 2 |
| | Glitch detector from gradient, modified 10 bit threshold register layout.
|
| #define | XSP3_FEATURE_GDET_LONG 3 |
| | Glitch detector from gradient, modified 10 bit threshold register layout and upto 511 pre-delay..
|
| #define | XSP3_FEATURE_LEAD_TAIL_LEAD 1 |
| | Include Correction for event lead in.
|
| #define | XSP3_FEATURE_LEAD_TAIL_GET_WIDTH(x) (((x)>>1)&3) |
| | Get feature of event lead/tail correction based on OTD width.
|
| #define | XSP3_FEATURE_LEAD_TAIL_WIDTH_NONE 0 |
| | No dependence on Width available.
|
| #define | XSP3_FEATURE_LEAD_TAIL_WIDTH4 1 |
| | Run ave lead/tail correction depends on width(3 downto 0).
|
| #define | XSP3_FEATURE_SERVO_BASE_NONE 0 |
| #define | XSP3_FEATURE_SERVO_BASE_PWL1 1 |
| | Single table (512 points) PWL servo.
|
| #define | XSP3_FEATURE_SERVO_BASE_PWL16 2 |
| | 16 table or 1 x 2048 points PWL servo.
|
| #define | XSP3_FEATURE_SERVO_BASE_DUAL 3 |
| | Combined linear (gross) and PWL (single table) servo.
|
| #define | XSP3_FEATURE_GET_FORMAT_A_NBITS(x) (((x)>>0)&3) |
| | Codes Nbits energy 12, 13,14Test source A from lower 2 bits.
|
| #define | XSP3_FEATURE_GET_FORMAT_A_AUX1(x) (((x)>>2)&3) |
| | Codes Aux1 functionality.
|
| #define | XSP3_FEATURE_AUX1_FUNC_NONE 0 |
| | None or Just good mode.
|
| #define | XSP3_FEATURE_AUX1_FUNC_DEBUG 1 |
| | Debug modes.
|
| #define | XSP3_FEATURE_AUX1_FUNC_THRES 2 |
| | Thresholded Good/bad and Debug.
|
| #define | XSP3_FEATURE_AUX1_FUNC_FULL 3 |
| | Full functionality.
|
| #define | XSP3_FEATURE_OUTPUT_FORMAT_ADDR32 0 |
| | Output is list of complete 32 address offsets for histogramming.
|
| #define | XSP3_FEATURE_OUTPUT_FORMAT_HEIGHTS64 1 |
| | Output is list of 64 bit words including processed event height and all auxiliary info.
|
| #define | XSP3_FEATURE_OUTPUT_FORMAT_RAW_AVERAGES 2 |
| | Output is Raw running avreages, needing lead and tail correction and then top-bottom subtraction.
|
| #define | XSP3_FEATURE_OUTPUT_FORMAT_DIFFERENCES 8 |
| | Output is ADC input data as a list of differences.
|
| #define | XSP3_FEATURE_FORMAT_B_HGT64_ACK_EOF 4 |
| | If XSP3_FEATURE_OUTPUT_FORMAT_HEIGHTS64 this bit implies there is an Acknowledge retry on the eond of frame markers.
|
| #define | XSP3_FEATURE_FORMAT_B_HGT64_ACK_TIME 1 |
| | If XSP3_FEATURE_OUTPUT_FORMAT_HEIGHTS64 this bit implies that the ackl and any frame data sends to previous frames total time.
|
| #define | XSP3_FEATURE_FORMAT_B_NO_ROI (1<<3) |
| | Output does not have Roi function.
|
| #define | XSP3_HGT64_SOF_GET_FRAME(x) (((x)>>0)&0xFFFFFF) |
| | Get time frmae from first (header) word.
|
| #define | XSP3_HGT64_SOF_GET_PREV_TIME(x) (((x)>>24)&0xFFFFFFFF) |
| | Get total integration time from previous time frame from first (header) word.
|
| #define | XSP3_HGT64_SOF_GET_CHAN(x) (((x)>>60)&0xF) |
| | Get channel number from first (header) word.
|
| #define | XSP3_HGT64_GET_HEIGHT(x) (((x)>>0)&0xFFF) |
| | Get event height.
|
| #define | XSP3_HGT64_GET_IN_RANGE(x) (((x)>>12)&1) |
| | Get in range signal.
|
| #define | XSP3_HGT64_GET_CAL_EVENT(x) (((x)>>13)&1) |
| | Get cal event flag.
|
| #define | XSP3_HGT64_GET_DIFF_NEGATIVE(x) (((x)>>14)&1) |
| | Get diff negative flag.
|
| #define | XSP3_HGT64_GET_RESET(x) (((x)>>15)&1) |
| | Get reset flag.
|
| #define | XSP3_HGT64_GET_GOOD_GRADE(x) (((x)>>16)&1) |
| | Get good grade flag.
|
| #define | XSP3_HGT64_GET_AUX2(x) (((x)>>17)&0xFFFF) |
| | Get Aux2 data.
|
| #define | XSP3_HGT64_GET_WIDTH(x) (((x)>>33)&0xFF) |
| | Get event or Reset Width.
|
| #define | XSP3_HGT64_GET_RESET_START(x) (((x)>>41)&0xF) |
| | Get Reset Start value.
|
| #define | XSP3_HGT64_GET_CHAN(x) (((x)>>48)&0xF) |
| | Get channel.
|
| #define | XSP3_HGT64_GET_AUX1(x) (((x)>>52)&0xFFF) |
| | Get AUX1 data.
|
| #define | XSP3_HGT64_GET_RESET_WIDTH(x) (((x)>>0)&0x3FF) |
| | Get Reset width which replaces event height.
|
| #define | XSP3_HGT64_DUMMY_RESET_LEN 0x400 |
| | Value to add to reset tick when a dummy reset occurs.
|
| #define | XSP3_HGT64_MASK_IN_RANGE (1L<<12) |
| | In Range mask.
|
| #define | XSP3_HGT64_MASK_CAL_EVENT (1L<<13) |
| | Mask for Calibration event.
|
| #define | XSP3_HGT64_MASK_DIFF_NEGATIVE (1L<<14) |
| | Mask for difference (top-bot) < 0.
|
| #define | XSP3_HGT64_MASK_RESET (1L<<15) |
| | Mask for real or reset.
|
| #define | XSP3_HGT64_MASK_GOOD_GRADE (1L<<16) |
| | Mask for good resolution grade.
|
| #define | XSP3_HGT64_MASK_RESET_DUMMY (1L<<45) |
| | Mask for dummy reset.
|
| #define | XSP3_DIFFS_CODE_DIFFS 0 |
| | Differences mode : Differences data.
|
| #define | XSP3_DIFFS_CODE_TIME_FRAME 1 |
| | Differences mode : Time frame first or change.
|
| #define | XSP3_DIFFS_GET_CODE(x) (((x)>>60)&0xF) |
| | Differences mode : Get Data code bits.
|
| #define | XSP3_DIFFS_TF_FIRST_MASK (1L<<59) |
| | Diffs Time frame is first word.
|
| #define | XSP3_DIFFS_TF_CHANGE_MASK 0 |
| | Diffs time frame is change of TF.
|
| #define | XSP3_DIFF_FIRST_CHAN(x) (((x)>>55)&0xF) |
| | Diff mode First word, extrac channel.
|
| #define | XSP3_DIFFS_TF_TIME_STAMP(x) ((x)&0x3FFFFFFF) |
| | Diffs time frame change Extract time stamp.
|
| #define | XSP3_DIFFS_TF_FRAME(x) (((x)>>30)&0xFFFFFF) |
| | Diffs time frame change Extract time frame.
|
| #define | XSP3_DIFFS_TF_ENABLE(x) (((x)>>(24+30))&1) |
| | Diffs time frame change Extract Count Enable.
|
| #define | XSP3_DIFFS_DATA_IDLE 0 |
| | Diffs 10 bit data special code for idle.
|
| #define | XSP3_DIFFS_DATA_START 1 |
| | Diffs 10 bit data special code for start.
|
| #define | XSP3_DIFFS_DATA_RESET 2 |
| | Diffs 10 bit data special code for End of Reset.
|
| #define | XSP3_DIFFS_DATA_GLOB_RST 3 |
| | Diffs 10 bit data special code for End of Global Reset.
|
| #define | XSP3_ITFG_SET_FRAMES(x) ((x)&0xFFFFFF) |
| | Set number of frames for internal TFG.
|
| #define | XSP3_ITFG_SET_TRIG_MODE(x) (((x)&7)<<24) |
| | Set trigger mode for internal TFG. See XSP3_ITFG_TRIG_MODE.
|
| #define | XSP3_ITFG_SET_GAP_MODE(x) (((x)&3)<<30) |
| | Set Miniumum mode for internal TFG.
|
| #define | XSP3_ITFG_MAX_NUM_FRAMES 0xFFFFFF |
| | Maximum number of time frames for internal TFG. Note that configurAtion of rest of system will usually limit the number of frame to less than this.
|
| #define | XSP3_ITFG_GET_FRAMES(x) ((x)&0xFFFFFF) |
| | Get number of frames for internal TFG.
|
| #define | XSP3_ITFG_GET_TRIG_MODE(x) (((x)>>24)&7) |
| | Get trigger mode for internal TFG.
|
| #define | XSP3_ITFG_GET_GAP_MODE(x) (((x)>>30)&3) |
| | Get fraem to frame gap mode for internal TFG.
|
| #define | XSP3_ITFG_TRIG_MODE_BURST 0 |
| | Run burst of back to back frames.
|
| #define | XSP3_ITFG_TRIG_MODE_SOFTWARE 1 |
| | Pause before every frame and wait for rising edge on CountEnb bit.
|
| #define | XSP3_ITFG_TRIG_MODE_HARDWARE 2 |
| | Pause before every frame and wait for rising edge on TTL_IN(1).
|
| #define | XSP3_ITFG_TRIG_MODE_SOFTWARE_ONLY_FIRST 5 |
| | Pause before first frame and wait for rising edge on CountEnb bit.
|
| #define | XSP3_ITFG_TRIG_MODE_HARDWARE_ONLY_FIRST 6 |
| | Pause before first frame and wait for rising edge on TTL_IN(1).
|
| #define | XSP3_ITFG_GAP_MODE_25NS 0 |
| | Minimal gap between frames. Care when using multiple boxes. Short cables and/or termination. 0 debounce time.
|
| #define | XSP3_ITFG_GAP_MODE_200NS 1 |
| | 200ns gap between frames. Use short cables and short (approx 10 cycle debounce time) when using multiple boxes.
|
| #define | XSP3_ITFG_GAP_MODE_500NS 2 |
| | 500ns gap between frames. Use approx 30 cycle debounce time when using multiple boxes.
|
| #define | XSP3_ITFG_GAP_MODE_1US 3 |
| | 1us gap between frames. Allows long cables and approx 70 cycle debounce time when using multiple boxes.
|
| #define | XSP3_UDP_SIG (SIGRTMAX-1) |
|
|
| #define | XSP3_FEATURE_TIMING_GEN_NONE 0 |
| | XSP3_FEATURS_TIMING_GEN Macros describing the internal timing generator
|
| #define | XSP3_FEATURE_TIMING_GEN_MINIMAL_ITFG 1 |
| | Timing Generator is minimal Internal TFG generating nframe all of same length, burst, started or all triggered.
|
|
|
| #define | XSP3_FEATURE_SCOPE_BIT15_GR_ONLY 0 |
| | XSP3_FEATURS_SCOPE Macros describing the scope mode features
|
| #define | XSP3_FEATURE_SCOPE_BIT15_ALT_ENB 1 |
| | Bit 15 of scope mode is uses alternate bits 3..0 to allow HistEnable to be seen.
|
Typedefs |
| typedef struct _xsp3_feature | Xspress3_features |
typedef struct
_xspress3_saved_config | Xspress3SavedConfig |
| typedef struct _UDPconnection | UDPconnection |
| typedef struct _XSPROI | XSP3Roi |
| typedef struct _ChannelDTC | ChannelDTC |
| typedef struct _Histogram | Histogram |
| typedef struct _XSP3Path | XSP3Path |
| typedef struct trigger_b_setttings | Xspress3_TriggerB |
| typedef struct trigger_c_setttings | Xspress3_TriggerC |
| typedef struct pileup_times_struct | XSP3_PileupTimes |
| typedef struct _fan_log | FanLog |
| typedef struct _fan_cont | FanControl |
Enumerations |
| enum | Xsp3ScopeOptions { Xsp3ScopeOpt_DelayStart = 1,
Xsp3ScopeOpt_ForceExtraDelay = 2,
Xsp3ScopeOpt_ExtraDelayOn0 = 4
} |
| enum | Xsp3TestPattern { Xsp3TP_Inc,
Xsp3TP_IncPlusPeaks
} |
Functions |
| int | xsp3_config (int ncards, int num_tf, char *baseIPaddress, int basePort, char *baseMACaddress, int nchan, int createmodule, char *modname, int debug, int card_index) |
| | Configure and initialise the complete xspress3 system.
|
| int | xsp3_do_config (int ncards, int num_tf, char *baseIPaddress, int basePort, char *baseMACaddress, int num_chan, int create_module, char *modname, int debug, int card_index) |
| | Configure the complete xspress3 system.
|
| int | xsp3_config_tcp (char femHostName[][XSP3_MAX_IP_CHARS], int femPort, int card, int chan, int debug) |
| | Configure the xspress3 system and create a 1Gb TCP socket link to each card in the system.
|
| int | xsp3_close (int path) |
| | Close all open paths in the system.
|
| char * | xsp3_get_error_message () |
| | Get the last error message that was generated by the xspress3 system.
|
| int | xsp3_get_revision (int path) |
| | Get firmware revision.
|
| int | xsp3_get_features (int path, int card, Xspress3_features *features) |
| | Return structure describing the hardware features enabled in the current firmware build.
|
| int | xsp3_get_num_chan (int path) |
| | Get the number of channels currently configured in the system.
|
| int | xsp3_set_num_chan (int path, int num) |
| | Set the number of channels to be used in system.
|
| int | xsp3_get_num_cards (int path) |
| | Get the number of xspress3 cards currently configured in the system.
|
| int | xsp3_get_chans_per_card (int path) |
| | Get the number of channels available per xspress3 card.
|
| int | xsp3_resolve_path (int path, int chan, int *thisPath, int *chanIdx) |
| | Determine which card and consequently the handle, a particular channel is configured on and the channel number within that card, given the top level system handle and the channel number.
|
| int | xsp3_set_trigger_b (int path, int detector, Xspress3_TriggerB *trig_b) |
| | Set the trigger B details.
|
| int | xsp3_get_trigger_b (int path, int chan, Xspress3_TriggerB *trig_b) |
| | Get the trigger B settings.
|
| int | xsp3_set_trigger_c (int path, int detector, Xspress3_TriggerC *trig_c) |
| | Set the trigger C details.
|
| int | xsp3_get_trigger_c (int path, int chan, Xspress3_TriggerC *trig_c) |
| | Get the trigger C settings.
|
| int | xsp3_set_trigger_b_ringing (int path, int chan, double scale_a, int delay_a, double scale_b, int delay_b) |
| | Set the trigger B ringing removal filter.
|
| int | xsp3_get_trigger_b_ringing (int path, int chan, double *scale_a, int *delay_a, double *scale_b, int *delay_b) |
| | Get the trigger B ringing removal filter.
|
| int | xsp3_trigger_b_get_ringing_params (int path, int *min_delay, int *max_delay) |
| | Get the trigger B ringing subtractor hardware limits.
|
| int | xsp3_get_max_num_chan (int path) |
| | Get the maxmimum number of channels currently available in system.
|
| int | xsp3_set_window (int path, int chan, int win, int low, int high) |
| | Set the scaler windows.
|
| int | xsp3_set_good_thres (int path, int chan, u_int32_t good_thres) |
| | Set the threshold for the good event scaler.
|
| int | xsp3_set_trigger_regs_b (int path, int chan, u_int32_t trigb_thres, u_int32_t trigb_timea, u_int32_t trigb_timeb) |
| | Set the raw trigger B registers, however the preferred method is to use xsp3_set_trigger_b.
|
| int | xsp3_set_trigger_regs_c (int path, int chan, u_int32_t trigc_otd_servo, u_int32_t trigc_thres) |
| | Set the raw trigger C registers, however the preferred method is to use xsp3_set_trigger_c.
|
| int | xsp3_set_chan_cont (int path, int chan, u_int32_t chan_cont) |
| | Set the channel control register.
|
| int | xsp3_set_format_reg (int path, int chan, u_int32_t format) |
| | Set the format register.
|
| int | xsp3_set_reset (int path, int chan, u_int32_t resetA, u_int32_t resetB, u_int32_t resetC) |
| | Set the reset registers A,B & C.
|
| int | xsp3_set_glitch (int path, int chan, u_int32_t glitchA, u_int32_t glitchB) |
| | Set the two glitch registers A and B.
|
| int | xsp3_set_servo (int path, int chan, u_int32_t servoA, u_int32_t servoB, u_int32_t servoC) |
| | Set the three servo registers A, B and C.
|
| int | xsp3_get_window (int path, int chan, int win, u_int32_t *low, u_int32_t *high) |
| | Get the scaler window settings.
|
| int | xsp3_get_good_thres (int path, int chan, u_int32_t *good_thres) |
| | Get the good event threshold.
|
| int | xsp3_get_trigger_regs_b (int path, int chan, u_int32_t *trigb_thres, u_int32_t *trigb_timea, u_int32_t *trigb_timeb) |
| | Get the raw trigger B registers, however the preferred method is to use xsp3_get_trigger_b.
|
| int | xsp3_get_trigger_regs_c (int path, int chan, u_int32_t *trigc_otd_servo, u_int32_t *trigc_thres) |
| | Get the raw trigger C registers, however the preferred method is to use xsp3_get_trigger_c.
|
| int | xsp3_set_cal_events (int path, int chan, int enable, int period, int avoid) |
| | Setup the Calibration event trigger generator.
|
| int | xsp3_get_glitch (int path, int chan, u_int32_t *glitchA, u_int32_t *glitchB) |
| | Get the glitch registers A & B.
|
| int | xsp3_write_reg (int path, int chan, int region, int offset, int size, u_int32_t *value) |
| | Write a series of values into the region registers for all or each specified channel.
|
| int | xsp3_read_reg (int path, int chan, int region, int offset, int size, u_int32_t *value) |
| | Read a series of values from the region registers for each specified channel.
|
| int | xsp3_get_servo (int path, int chan, u_int32_t *servoA, u_int32_t *servoB, u_int32_t *servoC) |
| | Get the servo control registers.
|
| int | xsp3_get_chan_cont (int path, int chan, u_int32_t *chan_cont) |
| | Get the channel control register.
|
| int | xsp3_get_format_reg (int path, int chan, u_int32_t *format) |
| | Get the format register.
|
| int | xsp3_get_format (int path, int chan, int *nbins_eng, int *nbins_aux1, int *nbins_aux2, int *nbins_tf) |
| | Get the format control parameters.
|
| int | xsp3_get_reset (int path, int chan, u_int32_t *resetA, u_int32_t *resetB, u_int32_t *resetC) |
| | Get the reset registers A, B and C.
|
| int | xsp3_write_glob_reg (int path, int card, int offset, int size, u_int32_t *value) |
| | Write a series of values into the global region register for all or each specified card.
|
| int | xsp3_read_glob_reg (int path, int card, int offset, int size, u_int32_t *value) |
| | Read a series of values from the global region register for each specified card.
|
| int | xsp3_read_raw_reg (int path, int card, u_int32_t address, int size, u_int32_t *value) |
| | Read a series of values from an address for each specified card.
|
| int | xsp3_set_clock_control (int path, int card, u_int32_t clock) |
| | Set the global clock control register.
|
| int | xsp3_get_clock_control (int path, int card, u_int32_t *clock) |
| | Get the global clock control register.
|
| int | xsp3_set_scope (int path, int card, u_int32_t scope_chn, u_int32_t scope_src, u_int32_t scope_nwd, u_int32_t scope_alt) |
| | Sets the scope mode registers.
|
| int | xsp3_get_scope (int path, int card, u_int32_t *scope_chn, u_int32_t *scope_src, u_int32_t *scope_nwd, u_int32_t *scope_alt) |
| | Get scope mode registers.
|
| int | xsp3_scope_settings_from_mod (int path) |
| | Get scope settings from data module and write into hardware.
|
| int | xsp3_scope_settings_to_mod (int path) |
| | Get scope mode options.
|
| int | xsp3_set_scope_options (int path, int card, Xsp3ScopeOptions options) |
| | Setup scope mode options.
|
| int | xsp3_set_scope_stream (int path, int card, int stream, u_int32_t chan, u_int32_t src, u_int32_t alt) |
| | Setup individual scope stream.
|
| int | xsp3_set_glob_timeA (int path, int card, u_int32_t time) |
| | Setup the triggering or time frame control register.
|
| int | xsp3_set_glob_timeFixed (int path, int card, u_int32_t time) |
| | Set the fixed time frame register.
|
| int | xsp3_get_glob_timeA (int path, int card, u_int32_t *time) |
| | Get the time frame register.
|
| int | xsp3_get_glob_timeFixed (int path, int card, u_int32_t *time) |
| | Get fixed time frame register.
|
| int | xsp3_dma_reset (int path, int card, u_int32_t function_mask) |
| | Reset the DMA engines.
|
| int | xsp3_dma_config_memory (int path, int card, int layout) |
| | Configure the memory.
|
| int | xsp3_dma_build_desc (int path, int card, u_int32_t func, XSP3_DMA_MsgBuildDesc *msg) |
| | Instruct PPC1 in the Virtex-5 to build a series of DMA descriptors.
|
| int | xsp3_dma_build_debug_desc (int path, int card, u_int32_t stream, XSP3_DMA_MsgBuildDebugDesc *msg) |
| | Instruct PPC1 in the Virtex-5 to build a series of DMA descriptors for debug.
|
| int | xsp3_dma_start (int path, int card, u_int32_t stream, XSP3_DMA_MsgStart *msgStart) |
| | Instruct PPC1 in the Virtex-5 to start a single DMA engine.
|
| int | xsp3_dma_build_test_pat (int path, int card, u_int32_t func, XSP3_DMA_MsgTestPat *msg) |
| | Instruct PPC1 in the Virtex-5 to build test patterns into the FFEM DRAM.
|
| int | xsp3_dma_print_data (int path, int card, u_int32_t func, XSP3_DMA_MsgPrint *msg) |
| | Instruct PPC1 in the Virtex-5 to build print data from DRAM.
|
| int | xsp3_dma_print_scope_data (int path, int card, XSP3_DMA_MsgPrint *msg) |
| | Instruct PPC1 in the Virtex-5 to build print scope data from DRAM.
|
| int | xsp3_dma_print_desc (int path, int card, u_int32_t stream, XSP3_DMA_MsgPrintDesc *msg) |
| | Instruct PPC1 in the Virtex-5 to build print the DMA descriptors This is printed onto the console for PPC1, accessible only via a serial cable onto the header on the FEM.
|
| int | xsp3_get_dma_status_block (int path, int card, XSP3_DMA_StatusBlock *statusBlock) |
| | Get the status and settings of all the DMA streams.
|
| int | xsp3_dma_check_desc (int path, int card, u_int32_t stream, XSP3_DMA_MsgCheckDesc *msg) |
| | This is called typically on an RX DMA Stream e.g.
|
| int | xsp3_dma_resend (int path, int card, u_int32_t stream, u_int32_t first, u_int32_t num) |
| | Instruct PPC1 in the Virtex-5 to reset the status in an existing set of descriptors so they can be sent again.
|
| int | xsp3_dma_read_status (int path, int card, u_int32_t stream_mask) |
| | Get the DMA status.
|
| int | xsp3_scope_wait (int path, int card) |
| | This function polls the DMA descriptors for the two scope DMA streams to check whether all the data has been transfered.
|
| int | xsp3_config_udp (int path, int card, char *femMACaddress, char *femIPaddress, int femPort, char *hostIPaddress, int hostPort) |
| | Configure all the parameters for a UDP connection to the xspress3 card.
|
| int | xsp3_config_histogram_udp (int path, int card, char *hostIPaddress, int hostPort, char *femIPaddress, int femPort) |
| | Configure the upd connection between the server and the xspress3 card and subsequently initializes a thread to perform the histogramming.
|
| int | xsp3_config_histogram_threads (int path, int card) |
| | Start event list processing threads for 1 or all cards in farm mode.
|
| int | xsp3_set_udp_port (int path, int card, int hostPort) |
| | Set the UDP port number.
|
| int | xsp3_set_udp_packet_size (int path, int card, int size_bytes) |
| | Set the UDP packet size in bytes.
|
| int | xsp3_read_scope_data (int path, int card) |
| | Read scope data from 10G ethernet using UDP protocol.
|
| int | xsp3_read_scope_data_int (int path, int card, int swap) |
| | Read scope data from 10G ethernet using UDP protocol.
|
| int | xsp3_create_data_module (int path, char *modname, int layout) |
| | Create the scope mode data module.
|
| int | xsp3_read_rdma_reg (int path, int card, int address, int size, u_int32_t *value) |
| | Read a series of values from the UPD core registers for each specified card.
|
| int | xsp3_write_rdma_reg (int path, int card, int address, int size, u_int32_t *value) |
| | Write a series of values into the UDP core registers for all or each specified card.
|
| int | xsp3_read_spi_reg (int path, int card, int address, int size, u_int32_t *value) |
| | Read a series of values from the SPI registers for each specified card.
|
| int | xsp3_write_spi_reg (int path, int card, int address, int size, u_int32_t *value) |
| | Write a series of values into the SPI registers for all or each specified card.
|
| int | xsp3_write_dram (int path, int card, int address, int size, u_int32_t *value) |
| | Write a series of values into DRAM memory for all or each specified card.
|
| int | xsp3_reset_10g_frame_counter (int path, int card) |
| | Reset the 10G frame counter to zero.
|
| int | xsp3_read_data_10g (int path, int card, int stream, int offset_bytes, int size_bytes, unsigned char *buff) |
| | Read data from the 10G ethernet using UDP protocol.
|
| int | xsp3_read_data_10g_receive (int path, int card, XSP3_DMA_StatusBlock *statusBlock, unsigned char *buff_base, u_int32_t first_frame, u_int32_t num_frames, u_int32_t *frame_flags) |
| | Data receiver for 10G UDP ethernet including resent frames.
|
| int | xsp3_write_playback_data (int path, int card, u_int32_t *buffer, size_t nbytes) |
| | Write playback data into DRAM via the 10G ethernet link.
|
| int | xsp3_write_data_10g (int path, int card, u_int32_t *buffer, int dst_stream, int offset_bytes, size_t nbytes) |
| | Write data into xspress3 utilising the 10G ethernet.
|
| int | xsp3_histogram_mkmod (int path, int chan, char *root_name, int num_tf) |
| | Creates Data modules to store the histogram data.
|
| int | xsp3_histogram_start (int path, int card) |
| | Start system and enable counting.
|
| int | xsp3_histogram_arm (int path, int card) |
| | Start system ready for histogramming but do not software enable histogramming.
|
| int | xsp3_histogram_start_count_enb (int path, int card, int count_enb) |
| | Start system and histogramming after resetting the UDP port and frame numbers as necessary.
|
| int | xsp3_histogram_stop (int path, int card) |
| | Stop histogramming.
|
| int | xsp3_histogram_clear (int path, int first_chan, int num_chan, int first_frame, int num_frames) |
| | Clears a section of the histogramming data buffer.
|
| int | xsp3_histogram_read4d (int path, u_int32_t *buffer, unsigned eng, unsigned aux, unsigned chan, unsigned tf, unsigned num_eng, unsigned num_aux, unsigned num_chan, unsigned num_tf) |
| | Read a 4 dimensional block of histogram data.
|
| int | xsp3_histogram_read3d (int path, u_int32_t *buffer, unsigned x, unsigned y, unsigned t, unsigned dx, unsigned dy, unsigned dt) |
| | Read a 3 dimensional block of histogram data with aux and chan combined into "y" to suit da.server.
|
| int | xsp3_histogram_read_chan (int path, u_int32_t *buffer, unsigned chan, unsigned eng, unsigned aux, unsigned tf, unsigned num_eng, unsigned num_aux, unsigned num_tf) |
| | Read a channel of histogram data.
|
| int | xsp3_histogram_write_test_pat (int path, Xsp3TestPattern type) |
| | Write a test pattern into histogramming memory.
|
| int | xsp3_histogram_get_dropped (int path, int chan) |
| | Read how many missed UDP packets of data have been detected since last start.
|
| int | xsp3_histogram_is_busy (int path, int chan) |
| | Check if the histogarmming thread is busy or waiting for data.
|
| int | xsp3_histogram_is_any_busy (int path) |
| | Check if any histogarmming thread for this system is busy or waiting for data.
|
| int | xsp3_scaler_check_progress (int path) |
| | This function checks how many time frames have been processed.
|
| int | xsp3_scaler_get_num_tf (int path) |
| | Read the maximum number of time frames of scaler data that can be stored with the current memory allocation within the FEM.
|
| int | xsp3_scaler_check_desc (int path, int card) |
| | This function checks the DMA descriptors for the Scaler stream to check how many time frames of scalers have been successfuly transfered to memeory.
|
| int | xsp3_scaler_read (int path, u_int32_t *dest, unsigned scaler, unsigned chan, unsigned t, unsigned n_scalers, unsigned n_chan, unsigned dt) |
| | Read a block of scaler data.
|
| int | xsp3_config_scaler (int path) |
| | Configure the scaler arrangement using the current memory allocation within the FEM.
|
| int | xsp3_scaler_dtc_read (int path, double *dest, unsigned scaler, unsigned chan, unsigned t, unsigned n_scalers, unsigned n_chan, unsigned dt) |
| | Read a block of dead time corrected scaler data.
|
| int | xsp3_hist_dtc_read4d (int path, double *hist_buff, double *scal_buff, unsigned eng, unsigned aux, unsigned chan, unsigned tf, unsigned num_eng, unsigned num_aux, unsigned num_chan, unsigned num_tf) |
| | Read a 4 dimensional block of dead time corrected histogram data and optionally return the dead time corrected scaler data.
|
| int | xsp3_setDeadtimeCalculationEnergy (int path, double energy) |
| | Set the energy for dead time energy correction.
|
| double | xsp3_getDeadtimeCalculationEnergy (int path) |
| | Get the energy for dead time correction.
|
| int | xsp3_setDeadtimeCorrectionParameters (int path, int chan, int flags, double processDeadTimeAllEventGradient, double processDeadTimeAllEventOffset, double processDeadTimeInWindowOffset, double processDeadTimeInWindowGradient) |
| | Set the parameters for dead time energy correction.
|
| int | xsp3_getDeadtimeCorrectionParameters (int path, int chan, int *flags, double *processDeadTimeAllEventGradient, double *processDeadTimeAllEventOffset, double *processDeadTimeInWindowOffset, double *processDeadTimeInWindowGradient) |
| | Get the parameters for dead time energy correction.
|
| int | xsp3_getDeadtimeCorrectionFlags (int path, int chan, int *flags) |
| | Get the flags only for dead time energy correction.
|
| int | xsp3_calculateDeadtimeCorrectionFactors (int path, u_int32_t *hardwareScalerReadings, double *dtcFactors, double *inpEst, int num_tf, int first_chan, int num_chan) |
| | Calculate the dead time correction factors from the scalers.
|
| int | xsp3_set_roi (int path, int chan, int num_roi, XSP3Roi *roi) |
| | Sets the regions of interest.
|
| int | xsp3_init_roi (int path, int chan) |
| | Initialise the regions of interest.
|
| MOD_IMAGE * | xsp3_mkmod (char *name, u_int32_t num_x, u_int32_t num_y, char *x_lab, char *y_lab, int data_float, mh_com **mod_head) |
| | Make a 2-d shared data module.
|
| MOD_IMAGE3D * | xsp3_mkmod3d (char *name, int num_x, int num_y, int num_t, char *x_lab, char *y_lab, char *t_lab, char **labels, int data_float, mh_com **mod_head) |
| | Make a 3-d shared data module.
|
| u_int32_t * | xsp3_mod_get_ptr (void *p, int x, int y, int t) |
| | Calculate the pointer to a given element of a 2-d or 3-d shared data module.
|
| struct xsp3_scope_data_module * | xsp3_scope_get_module (int path) |
| | Get a pointer to the scope data module.
|
| int | xsp3_system_start (int path, int card) |
| | Start the xspress3 system.
|
| int | xsp3_system_arm (int path, int card) |
| | Arm the xspress3 system, but in software time frame mode, counting is disabled.
|
| int | xsp3_histogram_continue (int path, int card) |
| | Continue counting from armed or paused when time framing is in software controlled (FIXED) mode.
|
| int | xsp3_histogram_pause (int path, int card) |
| | Pause counting in seriesof software timed frames.
|
| int | xsp3_system_start_count_enb (int path, int card, int count_enb) |
| | Start the xspress3 system with control over count enable in software framing mode.
|
| int | xsp3_set_run_flags (int path, int flags) |
| | Set the run mode flags.
|
| int | xsp3_get_run_flags (int path) |
| | Get the run mode flags.
|
| int | xsp3_get_bins_per_mca (int path) |
| | Get the number of bins per MCA configured in the xspress3 system.
|
| int | xsp3_bram_init (int path, int chan, int region, double scaling) |
| | Initialise the contents of the BRAM registers.
|
| int | xsp3_register_init (int path, int chan) |
| | Initialise the contents of the Channel Registers to as power up.
|
| int | xsp3_mdio_display (int path, int card) |
| | Read and print data from the AEL2005 10GE PHY.
|
| int | xsp3_mdio_set_connection (int path, int card, int conn) |
| | Set conection type to MDIO interface on FMC, via Aux connector or via FMC connector.
|
| int | xsp3_mdio_write (int path, int card, int port, int device, int addr, int data) |
| | Write data to the AEL2005 10GE PHY.
|
| int | xsp3_mdio_read (int path, int card, int port, int device, int addr, u_int32_t *data) |
| | Read data from the AEL2005 10GE PHY.
|
| int | xsp3_mdio_read_inc (int path, int card, int port, int device, u_int32_t *data) |
| | Read data from the AEL2005 10GE PHY andincrement internal address.
|
| int | xsp3_clocks_setup (int path, int card, int clk_src, int flags, int tp_type) |
| | Set up ADC data processing clocks source.
|
| int | xsp3_clocks_setup_int (int path, int card, int clk_src, int flags, int tp_type, int adc_clk_delay, int fpga_clk_delay) |
| | Set up ADC data processing clocks source with full control over delays.
|
| int | xsp3_set_ppc_debuglevel (int path, int card, int ppc1, int ppc2, int level) |
| | Setup the number of debug messages printed to the serial ports on the FEM directly from the embedded PowerPCs.
|
| int | xsp3_get_aux1_mode (int path, int chan, int *aux1_mode, int *aux1_thres) |
| | Get auxilliary data 1 mode as set by xsp3_format_run.
|
| int | xsp3_nbits_aux1 (int path, int res_mode) |
| | Get number of bits used by given aux1 special debug mode.
|
| int | xsp3_nbits_adc (int path, int adc_cont) |
| | Get the number of bits of ADC.
|
| int | xsp3_get_max_ave (int path, int chan) |
| | Get maximum number of samples used in the running average.
|
| int | xsp3_trigger_b_get_diff_params (int path, int *sep_offset, int *sep_max) |
| | Get the trigger B hardware limits determined by use of BRAM or SRL32 for diff1 and diff2 delay.
|
| int | xsp3_format_run (int path, int chan, int aux1_mode, int res_thres, int aux2_cont, int disables, int aux2_mode, int nbits_eng) |
| | Set format of the data to be histogrammed.
|
| int | xsp3_set_data_buffer (int path, int chan, u_int32_t *buffer, u_int32_t bufsiz) |
| | Set the location of the histogram buffer and buffer size in the xspress3 system.
|
| int | xsp3_set_data_module (int path, int chan, MOD_IMAGE *module, u_int32_t *buffer, u_int32_t bufsiz) |
| | Set the location of the data module, histogram buffer and buffer size in the xspress3 system.
|
| int | xsp3_get_num_tf (int path) |
| int | xsp3_set_num_tf (int path, int num_tf) |
| int | xsp3_set_scope_search (int path, int chan, u_int32_t scope_search) |
| | Set the value of the scope search register for specialist factory debug.
|
| int | xsp3_get_scope_search (int path, int chan, u_int32_t *scope_search) |
| | Get the value of the scope search register for specialist factory debug.
|
| int | xsp3_save_settings (int path, char *dir_name) |
| | Save all xspress3 settings into a series of files.
|
| int | xsp3_restore_settings (int path, char *dir_name, int force_mismatch) |
| | Restore all xspress3 settings from series of files.
|
| int | xsp3_get_glob_time_statA (int path, int card, u_int32_t *time) |
| | Get the timing status register A.
|
| int | xsp3_set_data_mux_cont (int path, int card, u_int32_t mux_cont) |
| | Set the ADC Data Mux register.
|
| int | xsp3_get_data_mux_cont (int path, int card, u_int32_t *mux_cont) |
| | Get the ADC Data Mux register.
|
| MOD_IMAGE * | xsp3_get_data_module (int path, int chan) |
| | Get a pointer to the data module in which the histogram data is stored for a particular channel.
|
| int | xsp3_i2c_read_adc_temp (int path, int card, float *temp) |
| | Read Temperature from all 4 LM75s on 1 or all ADC boards.
|
| int | xsp3_i2c_set_adc_temp_limit (int path, int card, int critTemp) |
| | Set over Temperature threshold for all 4 LM75s on 1 or all ADC boards.
|
| int | xsp3_write_fan_cont (int path, int card, int offset, int size, u_int32_t *value) |
| | Write a series of values into the fan controller data structure.
|
| int | xsp3_read_fan_cont (int path, int card, int offset, int size, u_int32_t *value) |
| | Read a series of values from the fan control data structure for the specified card.
|
| int | xsp3_playback_load_x2 (int path, int card, char *filename, int do_test, int do_scale, int do_swap) |
| | Load Playback data from an XSPRESS2 scope mode file.
|
| int | xsp3_playback_load_x3 (int path, int card, char *filename, int src0, int src1, int file_streams, int digital) |
| | Load Playback data from an XSPRESS3 scope mode file.
|
| int | xsp3_read_fem_config (int path, int card, int offset, int size, u_int8_t *value) |
| | Read a series of values from the FEM Config data structure for the specified card.
|
| int | xsp3_write_fem_config (int path, int card, int offset, int size, u_int8_t *value) |
| | Write a series of values into the FEM Config data structure.
|
| int | xsp3_features_unpack (int path, int card) |
| | Read the features registers and expand into the features structure.
|
| int | xsp3_has_soft_lut (int path, int chan, int region_num) |
| | Determine if the software processing has a given LUT/BRAM.
|
| int | xsp3_has_bram (int path, int chan, int region_num) |
| | Determine if the Firmware has a given BRAM.
|
| int | xsp3_write_soft_lut (int path, int chan, int region_num, int nwords, u_int32_t *data) |
| | Write Software lookup table equivalent to BRAM.
|
| int | xsp3_read_soft_lut (int path, int chan, int region_num, int nwords, u_int32_t *data) |
| | Read Software lookup table equivalent to BRAM.
|
| void * | read_and_histogram_hgt64 (void *args) |
| void * | read_and_save_diffs (void *args) |
| int | xsp3_soft_scaler_read (int path, u_int32_t *dest, unsigned first_scaler, unsigned first_chan, unsigned first_t, unsigned n_scalers, unsigned n_chan, unsigned dt) |
| | Read a block of software scaler data.
|
| int | xsp3_soft_scaler_clear (int path, int first_chan, int first_frame, int num_chan, int num_frames) |
| | Clear region of the software scalers data module.
|
| int | xsp3_config_soft_scaler (int path, char *mod_name, int num_tf) |
| | Build a shared data module for the software scalers.
|
| int | xsp3_get_has_soft_scalers (int path) |
| | Determine whether firmware requires scalers in software.
|
| int | xsp3_build_pileup_time (int path, int chan, int num_pairs, XSP3_PileupTimes *pileup_time, char *fname) |
| | Build the Pileup time lookup table for use in firmware or in software processing.
|
| int | xsp3_itfg_setup (int path, int card, int num_tf, u_int32_t col_time, int trig_mode, int gap_mode) |
| | Setup Internal time frame generator (TFG) for a series of equal length frames.
|
| int | xsp3_itfg_get_setup (int path, int card, int *num_tf, u_int32_t *col_time, int *trig_mode, int *gap_mode) |
| | Retrieve settings of the Internal time frame generator (TFG).
|
| int | xsp3_itfg_stop (int path, int card) |
| | Stop the Internal time frame generator (TFG).
|
| int | xsp3_has_itfg (int path, int card) |
| | Determine whether firmware includes an internal TFG.
|
| int | xsp3_has_reset_det (int path, int card) |
| | Determine whether firmware includes a Reset detector.
|
| int | xsp3_has_glitch_det (int path, int card, int *min_thres) |
| | Determine whether firmware includes a glitch detector.
|
| int | xsp3_has_scope_dig_alt0 (int path, int card) |
| | Determine whether firmware Alternatebit 3..0 controlling scope stream 0.
|
| int | xsp3_bram_size (int path, int chan, int region_num) |
| | Determine if the size of the given BRAM.
|
| int | xsp3_has_lead_tail_corr_width (int path, int chan, int region_num, int *num_t, int *num_wid) |
| | Determine the option code for event lead and tail correction type and and return layout.
|
| int | xsp3_has_lead_corr (int path, int card) |
| | Determine if the firmware has event lead-in corection configured.
|
| int | xsp3_has_servo_bi_linear_time (int path, int chan) |
| | Determine the option code for the bi-linear time version(s) of PWL servo.
|
| int | xsp3_set_global_reset_gen (int path, int card, int enable, int sync_mode, int det_reset_width, int hold_off_time, int gr_active_del, int gr_active_wid, int circ_offset) |
| | Configure the detector global reset generator.
|
| int | xsp3_get_disable_threading (int path) |
| | Get Disable multi threading flags.
|
| int | xsp3_set_disable_threading (int path, int flags) |
| | Set Disable multi threading flags.
|
Variables |
| int | xsp3_bram_size_table [XSP3_REGION_RAM_MAX+1] |
| int | xsp3_bram_width [XSP3_REGION_RAM_MAX+1] |
| const char * | xsp3_bram_name [XSP3_REGION_RAM_MAX+1] |
| char * | xsp3_feature_test_data_source_a [4] |
| char * | xsp3_feature_test_data_source_b [4] |
| char * | xsp3_feature_real_data_source [16] |
| char * | xsp3_feature_data_mux [16] |
| char * | xsp3_feature_inl_corr [16] |
| char * | xsp3_feature_reset_detector [16] |
| char * | xsp3_feature_reset_corr [16] |
| char * | xsp3_feature_glitch_detect [16] |
| char * | xsp3_feature_glitch_pad [16] |
| char * | xsp3_feature_trigger_b_l [4] |
| char * | xsp3_feature_trigger_b_m [4] |
| char * | xsp3_feature_trigger_c [16] |
| char * | xsp3_feature_trigger_extra [16] |
| char * | xsp3_feature_calibrator [16] |
| char * | xsp3_feature_neighbour_events [16] |
| char * | xsp3_feature_servo_base [16] |
| char * | xsp3_feature_run_ave3 [2] |
| char * | xsp3_feature_lead_tail0 [2] |
| char * | xsp3_feature_lead_tail12 [4] |
| char * | xsp3_feature_output_format [16] |
| char * | xsp3_feature_format_details_a01 [4] |
| char * | xsp3_feature_format_details_a23 [4] |
| char * | xsp3_feature_global_reset [16] |
| char * | xsp3_feature_timing_generator [16] |
| char * | xsp3_feature_scope_mode [16] |
